Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design

The large subthreshold leakage current of static CMOS logic circuits designed in modern nanometer-scale technologies is one of the main barriers for implementing ultra-low power digital systems. Subthreshold source-coupled logic (STSCL) circuits are based on an NMOS differential pair that is switching a constant tail bias current between the two output branches while biased at very low current levels. The power consumption of each STSCL gate depends on the tail bias current that can be controlled very well even for current levels in the range of few tens of pico-Amperes. The precise control on the power consumption of each gate, makes this topology very attractive for ultra-low power applications, where the power consumption of conventional static CMOS system is practically limited by the subthreshold leakage current. In this work, an analytical approach supported by simulation and measurement results will be presented to study the main issues in design of ultra-low power static CMOS and STSCL systems.