Organic thin-film transistors

Frédéric Zanella
EPFL, 2014
Thèse EPFL

Résumé

Organic molecules (i.e. carbon-based) have opened a new and rapidly-growing industrial field in the optoelectronic market bringing to this field a new dimension of thinness and flexibility. In this context, this thesis has focused on one particular building block of the vast and emerging field of organic electronics: the organic thin-film transistor (OTFT) which uses organic compounds as semiconductor. Whereas the OTFT-based circuits are not meant to compete with the silicon-based high-end industry (micro-processors...), their performance have already reached levels enabling their use in potential applications such as displays (e-paper, LCD, OLED) or radiofrequency identification (RFID) tags. The continuously growing number of available organic molecules exhibiting conductive, semi-conductive or insulating properties combined with the number of available deposition/patterning methods (e.g. gravure printing) gives more flexibility to the technology. These additional degrees of freedom raise two main questions: How to identify the most suitable OTFT platform for a given application and how to estimate its potential, as for instance in, of digital circuits? This thesis targets to answer to those questions. For this purpose, several OTFT platforms have been screened and their performance have been discussed and compared through standard figures of merit. The self-aligned nano-imprinted technology has demonstrated state-of-the-art sub-micrometer OTFTs on 4-inch flexible substrates. This made this platform the most suitable candidate for developing the potential evaluation framework. For that purpose, a static model suitable for the sub-micrometer OTFTs has been developed which embeds almost all known electrical aspects of OTFTs. Then the device-to-device discrepancy often observed in OTFTs has been studied and statistical modeling methods introduced. This allowed the simulation of sub-micrometer inverters performed with commercially available tools. Next, a statistical method has been developed to evaluate the potential of the sub-micrometer OTFTs for digital applications. Whereas the method concludes that these sub-micrometer OTFTs are not mature enough to make complex digital circuits, this methodology is technology-independent and may thus serve as a basis to characterize unipolar-logic printed electronics and be further extended to complementary-logic circuits. Last but not least, an automation effort has been undergone all along this thesis in order to increase the throughput for such demanding data analysis. The main outcome of this task is a user-friendly multi-analysis and parameter extraction platform.

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https://infoscience.epfl.ch/record/199132?ln=fr

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Frédéric Zanella
EPFL, 2014
Thèse EPFL

Résumé

Official source

https://infoscience.epfl.ch/record/199132?ln=fr

À propos de ce résultat

Concepts associés (13)

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Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high-integration density, but also to replace thin-film transistors in large-area electronics. This thesis investigates the use of wet-chemically grown ZnO nanowires for the fabrication of high-performance, low-voltage field-effect transistors (FETs). The first part of this thesis addresses the electrical characteristics of the wet-chemically grown ZnO nanowires. The as-grown ZnO nanowires are highly conductive due to a large charge-carrier concentration caused by dopants unintentionally incorporated into the ZnO nanowires during the synthesis. This large charge-carrier concentration makes it difficult to modulate the conductivity of the nanowires by an external electric field, so that the as-grown wires are not suitable for FETs. A post-growth annealing step is employed to dramatically reduce the charge-carrier concentration of the nanowires which makes it possible to fabricate FETs with useful characteristics. ZnO-nanowire FETs in a global back-gate geometry based on annealed ZnO nanowires have a transconductance of 300 nS, an on/off current ratio of 107 and a subthrehold slope of 500 mV/decade. The maximum field-effect mobility of the annealed ZnO nanowires is around 50 cm2/Vs. An important requirement to obtain good FET characterisitcs is to minimize the influence of the source and drain contact resistance on the total device resistance. The material used for the source and drain contacts in this thesis is aluminum. It is demonstrated that the use of a plasma treatment in the contact regions prior to the evaporation of the aluminum contacts can greatly influence the contact properties between ZnO and aluminum. An argon-plasma treatment locally increases the charge-carrier concentration in the ZnO. It is shown that the doping effect of the argon-plasma treatment can be exploited to reduce the contact resistance between alumiunm and ZnO and improve the electrical performance of the FETs. In the second part of this thesis, the influence of the ambient air on the electrical characteristics of the ZnO-nanowire FETs is investigated. The electrical conductivity of the FETs is strongly affected by the distinct atmospheric conditions, which makes it difficult to obtain reliable FET characteristics. The potential of a self-assembled monolayer (SAM) based on fluoroalkylphosphonic acid molecules to passivate the ZnO nanowires against the undesirable effects of the ambient and to stabilize the electrical performance of ZnO-nanowire FETs is demonstrated. The stabilizing effect is attributed to the formation of a densely packed, hydrophobic SAM on the surface of ZnO and aluminum oxide. The quality of the hydrophobic SAMs is confirmed by means of water-contact-angle measurements on SAM-covered ZnO single crystals that show a contact angle of more than 110°. The third part of this thesis is dedicated to the fabrication of high-performance ZnO-nanowire FETs with patterned metal top-gate electrodes. A top-gate fabrication process is developed that uses a very thin gate dielectric consisting only of an alkylphosphonic acid SAM that can be deposited from solution. The insulating quality of the SAM is investigated for top-gate FETs that utilize either gold or aluminum for the top-gate electrode. Gold top-gate FETs show a transconductance of 1 µS, an on/off current ratio of 107, and a steep subthreshold slope of 90 mV/decade. The thin gate dielectric makes it possible to operate the gold top-gate FETs at low voltages of 1 V and simultaneously reduces the undesired gate current by more than three orders of magnitude compared to gold top-gate FETs that have been fabricated without a gate dielectric (MESFETs). The gate current of the gold top-gate FETs with SAM gate dielectric is as low as 1 pA for gate-source voltages between -1 V and 0.5 V. When aluminum is used for the top-gate electrode, a hybrid dielectric is formed at the interface between the SAM and the aluminum, consisting of the SAM and a spontaneously formed aluminum oxide layer. Owing to the hybrid gate dielectric, the aluminum top-gate FETs are operated with gate currents below 1 pA for voltages up to 3 V. The top-gate fabrication process does not require temperatures above 160 °C, which makes it possible to fabricate FETs on unconventional substrates that cannot tolerate high temperatures, such as glass or flexible plastics. Integrated circuits on single ZnO nanowires that are fabricated on glass and plastic substrates are demonstrated. The maximum switching frequency of the inverters is 1 MHz.

EPFL2011

Chargement

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.

EPFL2005

Chargement

Electrical properties of functionalized nanowire field effect transistors

Ralf Thomas Weitz

The utilization of functional organic materials holds great promise for applications in electronic devices. Semiconducting organic molecules are frequently used as channel material in field effect transistors, due to the ease by which they can be assembled as such components, and the ease with which their properties can be specifically tailored. An extension of the use of organic materials in field effect transistors with the potential to substantially improve the performance of such devices is investigated in this thesis. It is the miniaturization of the functional parts of these devices, including their conductive channel or the gate dielectric, down to nanoscopic dimensions, which is important for their integration into complex device architectures. The materials under consideration offer advantages over conventional field effect transistor channels, including improved processibility, high mobility and electrical stability. The first part of the thesis is dedicated to the fabrication and electrochemical functionalization of nanoscopic field effect transistors comprising individual semiconducting single-walled carbon nanotubes. The combination of an ultra-thin gate dielectric based on an organic self-assembled monolayer is used for the fabrication of high-performance field effect transistors that show large on-state transconductance, as well as a large on/off ratio of 107, negligible hysteresis in the drain current, and a subthreshold swing that approaches the room temperature limit of 60 mV/decade. Two different types of self-assembled monolayers are used. The first, a silane-based self-assembled monolayer, is utilized to build field effect transistors in a global back gate geometry. This layout is useful for demonstrating the benefits of the use of a self-assembled monolayer for nanotube field effect transistors. Secondly, a gate dielectric incorporating a self-assembled monolayer composed of an alkane phosphonic-acid is exploited for the fabrication of high-performance field effect transistors with patterned aluminum gate electrodes. This geometry allows for the fabrication of more than one gate electrode per substrate and thus for the realization of logic circuits with all field effect transistors located on the same substrate. The technological relevance of nanotube field-effect transistors is proven by showing that nanotube field effect transistors can be cycled for more than 104 times between their on and off state and stored in ambient air for more than 200 days without degradation of their electrical performance. The electrochemical functionalization of individual single-walled carbon nanotubes with the organic coordination magnet Prussian Blue is investigated in the second part of this thesis. While this modification leaves metallic tubes unaffected, semiconducting SWCNTs become strongly p-doped during the electrochemical process. The temperature-dependent electrical behavior of Prussian Blue-functionalized semiconducting tubes can be understood by the freeze-out of the transfer of holes from the Prussian Blue below 150 K. In the third part of this thesis, novel core-cyanated perylene carboxylic diimides end-functionalized with substituents of varying flourine content and geometry are utilized as active material in air-stable n-channel thin film field- effect transistors. The relation between the thin-film structure and the air stability of the charge carrier mobility is investigated. Contrary to previous reports, it is found that the air stability is not related to the redox potential of the molecules. In addition, one of the compounds is used for the fabrication of field-effect transistors with a nanoribbon channel. These nanoribbons self-assemble from the solution phase, and, owing to their high crystalline order, field-effect transistors with mobilities of up to 0.2 cm2/Vs in air could be realized. The air stability of their mobility is found to be superior to that of thin-film transistors based on the same compound. Since the investigated perylene derivatives offer the possibility of fabricating thin-film as well as nanobelt field-effect transistors, they represent a valuable model system for the investigation of the relation between the crystalline order, mobility, stability and the performance of organic n-channel field-effect transistors. The last part is dedicated to a novel method for the fabrication of nanoscale polymer wires of diameters as small as 25 nm that offer potential as channel material for nanofiber field-effect transistors. These fibers emerge from a polymer solution during a standard spin-coating process. The fiber formation relies upon the Raleigh-Taylor instability of the spin-coated liquid film that arises due to a competition of the centrifugal force and the Laplace force induced by the surface curvature.

EPFL2008

Chargement

SOI mixed-mode design techniques and case studies

Marija Blagojevic

EPFL2005

EPFL2011

Electrical properties of functionalized nanowire field effect transistors

Ralf Thomas Weitz

EPFL2008