Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3 e(rms)(-) read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used.

Ultra Low Noise CMOS Image Sensors

Assim Boukhayma

CMOS Image Sensors (CIS) overtook the charge coupled devices (CCDs) in low noise performance. Photoelectron counting capability is the next step for CIS for ultimate low light performance and new imaging paradigms. This work presents a review of CMOS image sensors based on pinned photo diodes (PPDs). The latter includes the historical background, the PPD physics and the readout chain circuits used for low-noise performance. The physical mechanisms behind the random fluctuations affecting the signal at different levels of conventional CIS readout chains are reviewed and clarified. This thesis dedicates a particular focus to the readout circuit noise given that it precludes photoelectron counting in conventional CIS. A detailed analytical calculation of the temporal read noise (TRN) in conventional CIS readout chain is presented. The latter suggests different noise reduction techniques at process and circuit design level. Among the noise reduction techniques suggested by the analytical noise calculation, the increase of the oxide capacitance by using a thin oxide in-pixel amplifying transistor, for low 1/f noise, is suggested for the first time. A test chip designed in a 180 nm CIS process and embedding optimized readout chains exploiting the new pixels together with state-of-the-art 4T pixels optimized at process level for low 1/f noise. A mean input-referred noise of 0.4 e-rms has been measured. Compared with the state-of-the-art pixels, also present onto the test chip, the mean RMS noise is divided by more than 2. Based on these encouraging result, a full VGA (640H×480V) imager has been integrated in a standard CIS process. The presented imager relies on a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. The sensor chip features an input-referred noise histogram from 0.25 e-rms to a few e-rms peaking at 0.48 e-rms. This sub-0.5 electron noise performance is obtained with a full well capacity of 6400 e- and a frame rate that can go up to 80 fps. The VGA imager also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e-/s. Correlated multiple sampling (CMS) is a noise reduction technique commonly used in low noise CIS. This work presents an original design for CMS based on a passive switched-capacitor network, with a minimum number of capacitors. The proposed circuit requires no additional active circuitry, has no impact on the output dynamic range and does not need multiple analog-to-digital conversions. It was verified with transient noise simulations and shows a noise reduction in perfect agreement with ideal CMS. For a future perspective, the impact of the technology downscale on CIS sensitivity from an electronic read noise aspect is investigated. Active imaging in the Terahertz (THz) band is an emerging technology. Source modulation combined with a selective filtering can be used to reduce the noise in CMOS THz imagers. This work presents the first integration of a 1 kpixel CMOS THz imager integrating, in each pixel, a metal antenna with a MOS rectifier, low noise amplification and highly selective filtering, based on a switch-capacitor N-path filter combined with a broad band Gm-C filter. The latter has been tested successfully. An input-referred noise of 0.2 µV RMS corresponding to a total noise equivalent THz power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz.

EPFL2016

Design optimization for low light CMOS image sensors readout chain

Assim Boukhayma, Christian Enz

Email Print Request Permissions For a CIS readout chain based on 4T pixel, column amplification and CDS, we confirm that thermal noise can be reduced to be neglected compared to 1/f noise using parameters independent of the pixel design, namely column level gain, bandwidth control or correlated multiple sampling (CMS). Based on analytic noise calculation and simulation results using 180nm process, we show that CMS has no advantage over CDS for thermal noise reduction but offers slightly more 1/f noise reduction (about 20% less 1/f noise if high number of samples is used). 1/f and RTS noise originating from the in-pixel source follower transistor are reported to be the dominant noise sources in CIS readout chain. Based on analytic noise calculation, we demonstrate that, for a given CMOS process, the input referred 1/f noise is minimal for a unique pair of gate dimensions of the in-pixel source follower and we give its expression as a function of technological parameters.

2014

Recent trends in low-frequency noise reduction techniques for integrated circuits

Assim Boukhayma, Christian Enz

This paper presents the two main circuit techniques, namely autozeroing (AZ) and chopper stabilization (CS), that are used to reduce the 1/f noise and offset in amplifiers typically used in sensor electronics interfaces. After recalling their main properties, it looks into recent trends in circuit noise reduction techniques. First, the correlated multiple sampling (CMS) technique is presented as a generalization of AZ and correlated double sampling (CDS). Introduced in CMOS image sensors (CIS), it combines noise averaging and canceling and allows to further reduce the 1/f noise, but, like AZ, it is also ultimately limited by the aliasing of the broadband white noise. Another technique combining noise canceling and CS in a transimpedance amplifier (TIA) for bio-sensors is presented. It allows to maintain a low input impedance required by the TIA, while reducing the noise of the main transimpedance stage. CS is then used to cancel the noise of the following stages.

2015

Ultra Low Noise CMOS Image Sensors

Assim Boukhayma

EPFL2016