High-Speed ADC Design and Optimization for Wireline Links

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel loss. Analog-to-digital converter (ADC) based links consisting of high-speed ADCs and digital signal processors enable the implementation of powerful equalization algorithms in the digital domain. Such systems are implemented using advanced technology nodes to benefit from the power and area advantages that the advanced technology nodes provide for the digital blocks. In addition to the speed, the power efficiency and the compatibility with technology scaling are important parameters in the design of ADCs used in such systems. Successive approximation register (SAR) ADCs have become a popular choice in wireline applications because of their power efficiency and compatibility with advanced technology nodes due to consisting of mostly digital blocks.

This thesis focuses on high-speed SAR ADC design techniques to improve both conversion speed and power efficiency. First, a single-channel asynchronous SAR ADC design using a single comparator is presented to find out the achievable sampling rate with only one comparator. The 9-bit asynchronous SAR ADC prototype in 65 nm CMOS achieves 47.6 dB SNDR and 29.6 fJ/conv.-step figure-of-merit near Nyquist frequency at 222 MS/s and occupies an area of 0.017 mm2. Then, the use of comparator delay information for quantization is analyzed and a self-calibrated delay-based least significant bit extraction circuit, which achieves 3.35 dB SNDR for a 9-bit 200 MS/s with insignificant degradation in power consumption, speed, and area, is presented.

Next, loop-unrolled (LU) SAR ADC topology, which uses multiple comparators to improve the SAR loop delay, and comparator offset calibration techniques in LU-SAR ADCs are reviewed. Common-mode voltage variation in LU-SAR ADCs due to comparator kickback and the common-mode dependency of the comparator offset are addressed. A common-mode adaptive background offset calibration for LU-SAR ADCs is proposed. The proposed calibration scheme ensures that the comparators are calibrated at the same input common-mode voltage at which they each operate during the SAR conversion to prevent the common-mode dependent offset mismatch between the comparators. Besides, the common-mode variation immunity of the proposed calibration scheme is exploited to optimize the figure-of-merit of the LU-SAR ADC. The prototype 8-bit LU-SAR ADC manufactured in 28 nm FDSOI achieves 42.57 dB SNDR and 22.8 fJ/conv.-step figure-of-merit at 800 MS/s with near Nyquist frequency input and occupies an area of only 0.0037 mm2.

Lastly, an ADC-based receiver analog front-end (AFE) design in 28 nm FDSOI is presented and the feasibility of high order pulse amplitude modulation (PAM) is examined for a moderate-loss channel. The high order PAM compatible ADC-based AFE consists of a continuous-time linear equalizer and an 8 GS/s 8-way time-interleaved 7-bit SAR ADC with an embedded 2-tap feed-forward equalizer. All the equalization is implemented in the analog domain to avoid the circuit complexity and high power consumption of the digital equalization with high order modulation. The ADC-based AFE consumes 49.36 mW at 8 Gbaud, which corresponds to 1.54 pJ/bit at 32 Gb/s with PAM-16 and 2.06 pJ/bit at 24 GS/s with PAM-8.