Publication

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

Publications associées (72)

Graph Chatbot

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Connectez-vous pour utiliser Chat avec Graph Search

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Siang-Yun Lee

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

Mirjana Stojilovic, Ognjen Glamocanin, David Spielmann

State-of-the-art sensors for measuring FPGA voltage fluctuations are time-to-digital converters (TDCs). They allow detecting voltage fluctuations in the order of a few nanoseconds. The key building component of a TDC is a delay line, typically implemented ...

2023

Boolean Rewriting Strikes Back: Reconvergence- Driven Windowing meets Resynthesis

Giovanni De Micheli, Heinz Riener, Siang-Yun Lee

The paper presents a novel DAG-aware Boolean rewriting algorithm for restructuring combinational logic before technology mapping. The algorithm, called window rewriting, repeatedly selects small parts of the logic and replaces them with more compact implem ...

IEEE2022

Three-Input Gates for Logic Synthesis

Giovanni De Micheli, Mathias Soeken, Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2021

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

Francesco Regazzoni, Andrea Felice Caforio, Subhadeep Banik, Muhammed Fatih Balli

In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. In the past there have been numerous papers that have looked at circuit level implementation of block ciphers ...

IEEE2021

, ,

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

2021

, , ,

Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on m ...

AMER SOC MECHANICAL ENGINEERS2020

, , , , , ,

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-me ...

2020

The present invention relates to a reconfigurable logic circuit comprising - a first, second and third switching circuit arranged for receiving a first input bit, a second input bit and a third input bit, respectively, and each arranged for being configure ...

2020