At the end of scaling: 2D materials for computing and sensing applications

In the past half-century, the digital revolution completely changed the world we live in and the ways we experience it. Over this period, the underlying force supporting the continuous technological development has been the geometrical scaling of transistor dimensions, resulting in an exponential increase of the computation power density as well as a drastic decrease of chip cost. Approaching the end of the CMOS scaling era, the semiconducting industry faces enormous challenges to redefine its research priorities. Moreover, novel strict requirements on energy efficiency, system autonomy and remote sensing are posed by the development of the Internet of Things (IoT) networks. The quest for novel materials and device working principle is therefore more critical than ever. "More than Moore" devices aim to overcome the fundamental physical limitations of the MOSFET structure so to either replace or complement CMOS technology in a broad range of applications. Among this variegated research field, tunnel FETs have attracted a consistent interest in the last decades because of their steep turn on characteristic enabling the power supply scaling while maintaining a low standby power consumption. Several materials and TFET architectures have been demonstrated, with both promising results and great challenges in the quest for reducing the persisting performance gap with the established CMOS technology.

The aim of this thesis is to demonstrate the potential of two dimensional (2D) materials and heterojunctions for the realization of âMore than Mooreâ devices as well as for high sensitivity sensors. The continuously expanding family of 2D materials offers a huge catalog of electronic, mechanical and optical properties. The transition metal dichalcogenide (TMDC) group in particular includes a set of promising semiconductors with relatively large, number of layer dependent, band gap. MoS2 FET with excellent performance have been reported, while WSe2 has the potential of becoming the base for a true 2D CMOS platform.

MOSFET devices were fabricated starting from black phosphorous and WSe2 in order to investigate respectively fabrication strategies characterized by a reduced air exposure and the deposition of high k dielectric on 2D flakes. We then investigated the opportunities offered by the deterministic transfer of 2D flakes realizing both 3D/2D and 2D/2D heterojunction devices. The first reported VO2/MoS2 devices have been demonstrated obtaining a good rectifying characteristic and excellent, temperature tunable photosensitivity. Prototypes of three terminal devices based on this junction open the possibility for true VO2 based field effect devices. Finally, a heterojunction TFET based on WSe2/SnSe2 is presented. Our devices exhibit an excellent turn on characteristic and a direct comparison with the built-in, same flake WSe2 FET show how they outperform the MOSFET realized in the same material system. Moreover, we propose a new device combining the advantages of both MOSFET and TFET in a unique structure.

Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

Katherine Boucart

The down-scaling of conventional MOSFETs has led to an impending power crisis, in which static power consumption is becoming too high. In order to improve the energy-efficiency of electronic circuits, small swing switches are interesting candidates to replace or complement the MOSFETs used today. Tunnel FETs, which are gated p-i-n diodes whose on-current arises from band-to-band tunneling, are attractive new devices for low-power applications due to their low off-current and their potential for a small subthreshold swing. The numerical simulations presented in this thesis have been carried out using a non-local band-to-band tunneling model in Silvaco Atlas. Numerical simulations based on correct underlying models are important for emerging devices, since they can provide insights about optimization before fabrication is carried out, can aid the understanding of device physics through 1D and 2D cross sections, and can be the basis for the formation of an accurate compact model. In general, only CMOS-compatible materials and structures have been used in the Tunnel FET designs presented here. One goal of this thesis was to stay within the framework of what is possible in standard industrial nanoelectronics cleanrooms today, without requiring processes whose mastery lies many years in the future. For this reason, the focus of this thesis is on all-silicon devices, and heterostructures that incorporate other materials are only mentioned. In chapter three, the optimization of the static characteristics of a Tunnel FET is carried out, looking at gate structure (single or double), doping levels of each device region, gate dielectric permittivity, and silicon body thickness. A study of the reduction of the band gap at the tunnel junction is also presented, showing the resulting improvement in on-current and subthreshold swing. Chapter four introduces a new method for threshold voltage extraction in Tunnel FETs. This method has one key advantage over the commonly-used constant current threshold voltage extraction technique: it has a physical meaning. The transconductance method, which has already been used for conventional MOSFETs, pinpoints the Tunnel FET voltage at which the transition from strong control to weak control of the tunneling energy barrier width, and therefore the on-current, takes place. This is analogous to the threshold voltage in a conventional MOSFET which marks the transition from weak inversion to strong inversion at φs=2φF. It is found that Tunnel FETs have two threshold voltages, one in relation to the gate voltage, and the second in relation to the drain voltage, and each depends on the voltage applied at the opposite terminal. A length scaling study is carried out in chapter five, demonstrating the scaling limits of Tunnel FETs at gate lengths on the order of 10-20 nm, due to p-i-n diode leakage current that degrades the off-current. Tunnel FETs designed to have better electrostatic control of the tunnel junction by the gate can scale further before they hit this diode leakage limit at some small gate length. Chapter six presents an additive booster strategy for Tunnel FET optimization, and then uses the resulting optimized device as the basis of a parameter variation study. Here, one parameter is varied at a time, and the effects on the important characteristics (subthreshold swing, threshold voltage, and on-current) are evaluated. The parameters requiring the most control during fabrication are identified. Since Tunnel FETs are emerging devices, the most important future work will be to fabricate fully-optimized n- and p-type devices, and to develop accurate compact models for their incorporation into circuits.

EPFL2010

Ultrasensitive photodetectors based on monolayer MoS2

Metin Kayci, Andras Kis, Dominik Sebastian Lembke, Oriol López Sánchez, Aleksandra Radenovic

Two-dimensional materials are an emerging class of new materials with a wide range of electrical properties and potential practical applications. Although graphene(1) is the most well-studied two-dimensional material, single layers of other materials, such as insulating BN (ref. 2) and semiconducting MoS2 (refs 3,4) or WSe2 (refs 5,6), are gaining increasing attention as promising gate insulators and channel materials for field-effect transistors. Because monolayer MoS2 is a direct-bandgap semiconductor(7,8) due to quantum-mechanical confinement(7,9,10), it could be suitable for applications in optoelectronic devices where the direct bandgap would allow a high absorption coefficient and efficient electron-hole pair generation under photo-excitation. Here, we demonstrate ultrasensitive monolayer MoS2 phototransistors with improved device mobility and ON current. Our devices show a maximum external photoresponsivity of 880 AW(-1) at a wavelength of 561 nm and a photoresponse in the 400-680 nm range. With recent developments in large-scale production techniques such as liquid-scale exfoliation(11-13) and chemical vapour deposition-like growth(14,15), MoS2 shows important potential for applications in MoS2-based integrated optoelectronic circuits, light sensing, biomedical imaging, video recording and spectroscopy.

Nature Publishing Group2013

Mobility engineering and a metal–insulator transition in monolayer MoS2

Andras Kis, Branimir Radisavljevic

Two-dimensional (2D) materials are a new class of materials with interesting physical properties and applications ranging from nanoelectronics to sensing and photonics. In addition to graphene, the most studied 2D material, monolayers of other layered materials such as semiconducting dichalcogenides MoS2 or WSe2 are gaining in importance as promising channel materials for field-effect transistors (FETs). The presence of a direct bandgap in monolayer MoS2 due to quantum-mechanical confinement allows room-temperature FETs with an on/off ratio exceeding 10(8). The presence of high-kappa dielectrics in these devices enhanced their mobility, but the mechanisms are not well understood. Here, we report on electrical transport measurements on MoS2 FETs in different dielectric configurations. The dependence of mobility on temperature shows clear evidence of the strong suppression of charged-impurity scattering in dual-gate devices with a top-gate dielectric. At the same time, phonon scattering shows a weaker than expected temperature dependence. High levels of doping achieved in dual-gate devices also allow the observation of a metal-insulator transition in monolayer MoS2 due to strong electron-electron interactions. Our work opens up the way to further improvements in 2D semiconductor performance and introduces MoS2 as an interesting system for studying correlation effects in mesoscopic systems.

Nature Publishing Group2013

Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

Katherine Boucart

EPFL2010