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Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

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Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

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Chattez avec Graph Search

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Gain-Cell Embedded DRAMs: Modeling and Design Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Gain-Cell Embedded DRAMs: Modeling and Design Space

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Associativity-agnostic in-cache computing memory architecture optimized for multiplication