Publication
A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The scheme utilizes an identical pseudo-random sequence for every image column, therefore reducing in-pixel hardware complexity and allowing measurement matrix generation in a single clock cycle. As a result, high frame rates and low power consumption are achievable with an acceptable reduction in raw image quality for many practical video applications. Physical IC design issues such as device mismatch, noise and non-linearity, are analyzed and their effects on compressed image acquisition are presented and discussed. As a proof-of-concept, specialized pixels, Comparator-Based Switched Capacitor readout and Column-Parallel Differential Cyclic-ADCs are designed in a 0.18μm standard CMOS technology. The simulation results of the proposed circuit show that a 256×256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The proposed scheme can easily be applicable in different circuit design solutions and scaled towards newer technology nodes and higher image resolutions.