Method for speeding up boolean satisfiability

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Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

IEEE2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

Edoardo Charbon, Pouyan Keshavarzian, Francesco Gramuglia, Mario Stipcevic

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in or ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Benoît Walter Denkinger

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023

Integrated Electronics for Deep Implants to Remotely Monitor Hemodynamics

Mustafa Besirli

The integration of technology in the medical field has greatly improved accuracy in diagnoses, thus leading to more effective treatments. Wearable and implantable medical devices offer great potential for remote patient monitoring, particularly for heart f ...

EPFL2023

Miniaturised, Wireless and Distributed Neural Interface Toward Cortical Visual Prosthesis

Gian Luca Barbruni

Over the last decades, implantable neural interfaces have been extensively explored and effectively deployed to address neurological and mental health disorders. The existing solutions present several limitations. Firstly, the physical size of the implanta ...

EPFL2023

Design and manufacture of edible microfluidic logic gates

Dario Floreano, Bokeon Kwak, Shuhang Zhang

Edible robotics is an emerging research field with potential use in environmental, food, and medical scenarios. In this context, the design of edible control circuits could increase the behavioral complexity of edible robots and reduce their dependence on ...

IEEE2023

500 MHz high resolution proximity sensors with fully integrated digital counter

Giovanni Boero, Nergiz Sahin Solmaz, Reza Farsi

We report on the design and characterization of two inductive proximity sensors based on LC oscillators operating at 500 MHz. The distance from the target is obtained by measuring the oscillation frequency variation. Both sensors contain an off-chip LC res ...

ELSEVIER SCI LTD2023

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Guilherme Migliato Marega

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

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A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022