SR Latch and D Flip-Flop: Memory Elements in Logic Systems

In course

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Description

This lecture covers the operation of SR latch and D flip-flop in logic systems. The SR latch has a forbidden state due to metastability issues, while the D flip-flop stores data based on a clock signal. The lecture also discusses multiplexers, demultiplexers, XOR gates, and tristate gates.

Instructor

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Official source

https://mediaspace.epfl.ch/media/0_c69t6h8o

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Ontological neighbourhood

Electrical engineering

Electronic engineering: Digital electronics

Physics

Physical quantities: Topics in physical quantities

Logic

Classical logic: First-order logic

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