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The upgrade of the MALTA DMAPS designed in Tower 180 nm CMOS Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x10(15) 1 MeVn(eq)/cm(2). The effectiveness of these changes have been demonstrated in recent measurements with a small-scale Mini-MALTA demonstrator chip. Multiple changes in the digital periphery are proposed: The asynchronous address generator will be revised to provide more control over the pulse length. The Synchronization memory will be upgraded with the goal of achieving a sub-nanosecond timing resolution. Serial chip to chip data transfer will be prototyped, in order to gauge the plausibility of implementation on a future full sized chip. Apart from these changes, research of the overall sensor architecture will be discussed as well.
Johanna Zikulnig, Jürgen Kosel
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