Computational Imaging SPAD Cameras

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the raw pixel data and reduce the amount of information that needs to be read from the sensor. With the emergence of large format single-photon avalanche diode (SPAD) imagers, the need for on-chip processing has become more evident, as the output data rate of such detectors is pushing the limit of even modern interfaces.The aim of the thesis is to develop sensor architectures for computational imaging that overcome limitations of conventional SPAD imagers and can operate at high frame rates with manageable output data rates. Three sensors are designed in different technology nodes, from 180nm 2D to 3D-stacked 45/22nm and 180/16nm, backside and front-side illuminated.A novel token-based readout technique is developed to improve system frame rate by reducing the readout time through omission of dark pixels. The technique is implemented in kiloPhase, a 32x32 gated SPAD imager with vector processing capabilities that can achieve 4.38ns gates and can operate at 227fps in 10bit intensity mode, a 12% increase compared to conventional readout. An improved, massively parallel version of the architecture is implemented in MegaPhase, a 1-megapixel SPAD imager consisting of 16384 processing cores that can perform addition and multiplication operations on the raw pixel data. The SPADs can be binned with multiple granularities to increase the pixel dynamic range and reduce the required exposure time. Simulations show a frame rate increase of up to 170x when operating as an intensity imager and 56x in gated fluorescence lifetime imaging (FLIM) mode.Finally, UltraPhase, the first fully reconfigurable SPAD processing architecture is developed and consists of 18 independent processors running at 140MOPS with a power consumption of less than 94.6GOPS/W. Each processor can execute up to 256 instructions per program and contains a reconfigurable front end that can implement a wide range of combinatorial functions and a timing module that can be configured to measure photon arrival timestamps.