Publications related to Logic family

Paolo Ienne, Grace Zgheib, David Novo Bruna, Hadi Parandeh Afshar

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

2014

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Shashi Kanth Bobba, Michele De Marchi

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

For more than four decades, Complementary Metal-Oxide- Semiconductor (CMOS) Field Effect Transistors (FETs) have been the baseline technology for implementing digital computation systems. CMOS transistors natively implement Not-AND ...

2014

CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition

Yusuf Leblebici, Sung Mo Kang

The fourth edition of CMOS Digital Integrated Circuits: Analysis and Design continues the well-established tradition of the earlier editions by offering the most comprehensive coverage of digital CMOS circuit design, as well as addressing state-of-the-art ...

McGraw-Hill Higher Education2014

Accurate RF modeling of nanoscale MOSFET using BSIM6 including low levels of inversion

Christian Enz, Maria-Anna Chalkiadaki

Nanoscale CMOS devices display very high peak transit frequency Ft of several hundreds of GHz. This feature can be exploited for reducing power consumption by shifting the operating point towards moderate or eventually weak inversion where the Ft still rea ...

Elsevier2014

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS tra ...

2014

Compact Modeling of Homojunction Tunnel FETs

Mihai Adrian Ionescu, Wladyslaw Grabinski, Antonios Bazigos, Luca De Michielis, Cem Alper, Arnab Biswas, Nilay Dagtekin

Aggressive scaling of the supply voltage reduces the energy needed for switching of standard CMOS devices. However, advanced CMOS technologies are facing two main problems that consequently lead to higher power consumption: the complexity of a further supp ...

IEEE2014

Shallow donor and deep DX-like center in InAlN layers nearly lattice-matched to GaN

Nicolas Grandjean, Jean-François Carlin, Marcel Py, Lorenzo Lugani

Nonintentionally doped 200-nm-thick In0.16Al0.84N/n(+)-GaN samples were grown by metal-organic vapor phase epitaxy and used for the electrical characterization of InAlN. In the temperature range 180-400 K, the forward current of Schottky diodes is dominate ...

Amer Physical Soc2014

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Logic family

Non-LUT field-programmable gate arrays

Organic thin-film transistors

Nanowire systems: technology and design (invited paper)

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis

CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition

Accurate RF modeling of nanoscale MOSFET using BSIM6 including low levels of inversion

Ultra-Low-Temperature Silicon and Germanium-on-Silicon Avalanche Photodiodes

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Compact Modeling of Homojunction Tunnel FETs

Shallow donor and deep DX-like center in InAlN layers nearly lattice-matched to GaN

Graph Chatbot

Chat with Graph Search

Non-LUT field-programmable gate arrays

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis

Ultra-Low-Temperature Silicon and Germanium-on-Silicon Avalanche Photodiodes

Organic thin-film transistors

Nanowire systems: technology and design (invited paper)

CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition

Accurate RF modeling of nanoscale MOSFET using BSIM6 including low levels of inversion

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Compact Modeling of Homojunction Tunnel FETs

Shallow donor and deep DX-like center in InAlN layers nearly lattice-matched to GaN