Publications related to BiCMOS

Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

Elmira Shahrabi, Yusuf Leblebici, Jury Sandrini, Tugba Demirci, Mahmoud Hadad, Behnoush Attarimashalkoubeh

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180 nm CMOS technology chips. The proposed integration method enables low- cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory sy ...

Ieee2016

A low-power high-sensitivity single-chip receiver for NMR microscopy

Giovanni Boero, Jens Anders

In this paper, we present a fully-integrated receiver for NMR microscopy applications manufactured in a 0.13 mu m CMOS technology. The design co-integrates a 10-turn planar detection coil together with a complete quadrature, low-IF downconversion receiver ...

Academic Press Inc Elsevier Science2016

A CMOS Amperometric System for Multi-Neurotransmitter Detection

Giovanni De Micheli, Sandro Carrara

In vivo multi-target and selective concentration monitoring of neurotransmitters can help to unravel the brain chemical complex signaling interplay. This paper presents a dedicated integrated potentiostat transducer circuit and its selective electrode inte ...

Ieee-Inst Electrical Electronics Engineers Inc2016

RF Small-Signal and Noise Modeling Including Parameter Extraction of Nanoscale MOSFET From Weak to Strong Inversion

Christian Enz, Maria-Anna Chalkiadaki

The downscaling of CMOS processes has led to devices with an impressive RF performance. Advanced nanoscale RF MOSFETs present very high transit frequency, which can be traded off with lower power consumption, by shifting the operating point towards the wea ...

Ieee-Inst Electrical Electronics Engineers Inc2015

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Hassan Ghasemzadeh Mohammadi

Controllable-Polarity Silicon Nanowire Transistors (CP-SiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the on-line configuration ...

Institute of Electrical and Electronics Engineers2015

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

Pierre-André Farine, Rafal Tomasz Dlugosz

The paper presents a new initialization mechanism based on a Convex Combination Method (CCM) for Kohonen self-organizing Neural Networks (NNs) realized in the CMOS technology. A proper selection of initial values of the neuron weights exhibits a strong imp ...

Elsevier Science Inc2015

10.3 A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces in 40nm CMOS

Seyed Armin Tajalli, Yusuf Leblebici, Kiarash Gharibdoust

Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing system. Memory systems typically apply ...

IEEE2015

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Jury Sandrini, Somayyeh Rahimian Omam, Maxime Victor Thammasack

Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of ...

IEEE2015

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BiCMOS

Anomalous visualization of sub-2 THz radiation on silicon- based CMOS and CCD sensors

Design methodology for low power RF LNA based on the figure of merit and the inversion coefficient

Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

A low-power high-sensitivity single-chip receiver for NMR microscopy

A CMOS Amperometric System for Multi-Neurotransmitter Detection

RF Small-Signal and Noise Modeling Including Parameter Extraction of Nanoscale MOSFET From Weak to Strong Inversion

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

10.3 A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces in 40nm CMOS

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

Graph Chatbot

Chat with Graph Search

Design methodology for low power RF LNA based on the figure of merit and the inversion coefficient

Anomalous visualization of sub-2 THz radiation on silicon- based CMOS and CCD sensors

Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

RF Small-Signal and Noise Modeling Including Parameter Extraction of Nanoscale MOSFET From Weak to Strong Inversion

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

A low-power high-sensitivity single-chip receiver for NMR microscopy

A CMOS Amperometric System for Multi-Neurotransmitter Detection

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

10.3 A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces in 40nm CMOS