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Concept
Frequency divider
Summary
A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, , and generates an output signal of a frequency:
where is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both analog and digital applications.
Analog frequency dividers are less common and used only at very high frequencies. Digital dividers implemented in modern IC technologies can work up to tens of GHz.
A regenerative frequency divider, also known as a Miller frequency divider, mixes the input signal with the feedback signal from the mixer.
The feedback signal is . This produces sum and difference frequencies , at the output of the mixer. A low pass filter removes the higher frequency, and the frequency is amplified and fed back into the mixer.
A free-running oscillator which has a small amount of a higher-frequency signal fed to it, will tend to oscillate in step with the input signal. Such frequency dividers were essential in the development of television.
It operates similarly to an injection locked oscillator. In an injection-locked frequency divider, the frequency of the input signal is a multiple (or fraction) of the free-running frequency of the oscillator. While these frequency dividers tend to be lower power than broadband static (or flip-flop-based) frequency dividers, the drawback is their low locking range. The ILFD locking range is inversely proportional to the quality factor (Q) of the oscillator tank. In integrated circuit designs, this makes an ILFD sensitive to process variations. Care must be taken to ensure the tuning range of the driving circuit (for example, a voltage-controlled oscillator) must fall within the input locking range of the ILFD.
For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at 1/2 the rate of the input clock, the next bit at 1/4 the rate, the third bit at 1/8 the rate, etc.
Official source
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