Concept

Bus (computing)

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Bus (computing)

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Bus reversable orthogonal differential vector signaling codes

Realization and optimization of bus bar current transducers based on Hall effect sensors

Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication

Confluence: unified instruction supply for scale-out servers

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology

Finite state encoders and decoders for vector signaling codes

An Ultra-High Speed Emulator Dedicated to Power System Dynamics Computation Based on a Mixed-Signal Hardware Platform

An Enhanced Design Methodology for Resonant Clock Trees

Bus reversable orthogonal differential vector signaling codes

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

An Enhanced Design Methodology for Resonant Clock Trees

Realization and optimization of bus bar current transducers based on Hall effect sensors

Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication

Confluence: unified instruction supply for scale-out servers

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

An Ultra-High Speed Emulator Dedicated to Power System Dynamics Computation Based on a Mixed-Signal Hardware Platform

Finite state encoders and decoders for vector signaling codes

26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology