Test of VLSI Systems: Combinational and Sequential ATPG

This lecture covers the necessity and costs of testing VLSI systems, fault modeling, simulation, and test quality measurement. It delves into generating test vector patterns, structural vs. functional tests, scan design, search space abstractions, and the five values algebra. The computational burden of functionally and structurally testing a 64-bit adder is discussed, along with the Automatic Test-Pattern Generator (ATPG) algorithm, search space abstractions, and Roth's 5-valued algebra. Path sensitization methods, D-algorithm, backward and forward implications, fault cones, and D-frontiers are explained. The lecture concludes with examples of circuit path sensitization and the implementation of time-frame expansion for fault detection in sequential circuits.