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Related lectures (30)
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Semicustom RTL Design: Frontend with Synthesis
Covers the fundamentals of VLSI design, focusing on the semi-custom design flow.
FPGA Programming with Speedgoat: A Comprehensive Overview
Covers FPGA programming with Speedgoat, focusing on synthesis, design practices, and practical examples.
VHDL for Simulation & Testbenches
Explores VHDL for simulation, debugging, time modeling, event-based simulation, and testbench creation in digital system design.
Semicustom RTL Design: Design Flow and Standard Cells
Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.
Field Programmable Gate Arrays (FPGAs)
Covers the basic principles and architecture of Field Programmable Gate Arrays (FPGAs) and their implementation options for digital circuits.
FPGA Programming with Speedgoat: Real-Time Signal Processing
Focuses on implementing a square function generator using Speedgoat FPGA technology and real-time signal processing techniques.
Simulation-Based Verification
Explores simulation-based verification in VLSI systems using compiled-code and event-driven algorithms.
Generating a CLK Generator (PLL) IP in Vivado
Covers the process of generating a Clock Generator (PLL) IP in Vivado using the Clocking Wizard tool.
Digital Logic Circuits: CMOS and Verilog Modeling
Discusses digital logic circuits, focusing on CMOS technology and Verilog modeling techniques.
VHDL for Synthesis
Covers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.