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Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding

Related publications (33)

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Emulating Multimemristive Behavior of Silicon Nanowire-Based Biosensors by Using CMOS-Based Implementations

Sandro Carrara, Junrui Chen, Kapil Bhardwaj

The research presented in this article draws inspiration from previous efforts aimed at replicating the functions of various solid-state memristors using a variety of materials. The memristor circuit emulator serves as a cost-effective tool for circuit des ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Design and manufacture of edible microfluidic logic gates

Dario Floreano, Bokeon Kwak, Shuhang Zhang

Edible robotics is an emerging research field with potential use in environmental, food, and medical scenarios. In this context, the design of edible control circuits could increase the behavioral complexity of edible robots and reduce their dependence on ...

IEEE2023

Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures

Edoardo Charbon, Harald Arjan Robert Homulle, Fabio Sebastiano

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed und ...

2018

Charge-Based Distortion Analysis of Nanoscale MOSFETs

Christian Enz, Alessandro Pezzotta, Francesco Chicco

This paper presents a study of MOSFETs' linearity, exploiting a simplified version of the charge-based EKV model. It allows to deduce analytically the one-tone and two-tone harmonic distortions introduced by the nonlinear ID-VG MOSFET characteristic as a f ...

2018

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced wi ...

Institute of Electrical and Electronics Engineers2016

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This paper explores the potential and limitations of analog integrated circuit techniques for the simulation of low-loss or lossless 1D or 2D transmission mediums. In this approach, a transmission line is mapped into a ladder consisting of N identical LC e ...

Springer Verlag2016

Signaling in 3-D integrated circuits, benefits and challenges

Somayyeh Rahimian Omam

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuit ...

EPFL2015

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

Alexandre Schmid, Seyed Armin Tajalli, Mahsa Shoaran, Yusuf Leblebici

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

2015

A 15 mu W 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB

Catherine Dehollain

A low power SAR logic-based resistive sensor readout circuit is proposed. A high sensitivity thermistor is used for local temperature measurements. The need for a low-noise front-end voltage amplifier is avoided by employing time-domain operation. In each ...

Institute of Electrical and Electronics Engineers2014

Capteur CentoNewton-Bd' - ajustement

Thomas Maeder, Caroline Jacq

Ce document décrit l'ajustement de la version Bd' du capteur de force CentoNewton. Malgré les corrections déjà introduites, l'itération Bd a toujours un problème d'ajustement de l'offset, en raison du mauvais appariement des résistances d'ajustement grossi ...

EPFL-LPM2014