Integration of Engineered Source and Drain Extensions in Double Gate Mosfet with Sub-32nm Channel Length

Since the advent of CMOS technology, the semiconductor industry has been successful in achieving continuously improved performance. The feature size of the most important electronic device, the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), has already be reduced from about 10 µm to sub 100 nm regime during the last 30 years. The enormous miniaturization and integration of MOSFET devices has made possible a dramatic development in microelectronics. However, many challenges exit and have to be addressed to achieve sub-30 nm devices: increased Source/Drain (S/D) resistances, excessive gate oxide leakage and deteriorated device performance due to short channel effects (SCE). In order to keep Moore's Law living, device scaling down is not any more enough. To keep pace with scaling several technological booster have been introduced such as SiGe or Metallic material for S/D, high-k dielectric as a gate material, SOI or strained silicon for channel material and multi gate architecture. Double Gate (DG) architecture is believed to be used for beyond 22 nm node because of its advantage in terms of preserving the electrostatic integrity. The key issue introduced by DG is misalignment which can be overcome by fabricating self aligned structure. However this device suffers from the series resistance. Hence S/D can be engineered either by introducing new material like SiGe or Ge (Band gap engineering) or silicidation induced Dopant Segregation (DS). In both case, current can be improved by enhanced carrier injection from source to channel and reducing series resistance. This thesis includes the method to integrate the S/D in DG structure. We start with identifying the conditions (implantation and annealing) to achieve high active dopants in thin film S/D and SiGe integrated S/D. In additions to this, means to implant the extension in scaled devices are explored. In the second step, the processes and conditions are developed for etching, epitaxy and silicidation. It is demonstrated that contact resistivity down to 0.1 Ω.µm2 can be obtained by integrating PtSi S/D suitable for p-MOSFETs. The final DG devices after integrating S/D are characterized and analyzed. The electric potential of the architecture DG in terms of control of SCE and mobility are exploited. The transport mechanism (Thermionic or Tunneling) is understood by performing the static device measurement at low (77 °K) to high (363 °K) temperatures. Schottky barrier heights of as low as 0.1eV and access resistance of 250 Ω.µm are demonstrated with our proposed and fabricated devices, thanks to DS metallic S/D. These results can be considered as being at the level of the state of the art for metallic S/D device today.

Ordered nanostructures on silicon substrates

Jelena Vukajlovic Plestina

Silicon is today the main material used in electronics. It is a very advanced and mature technology. It is therefore clear that new technological concepts and materials should be introduced through the integration on the silicon platform. III-V semiconductors, such as GaAs and InAs, are high performance semiconductors, with direct bandgap and high carrier mobility, what makes them very prominent candidates for future electronics and optoelectronics. Lattice, thermal and polarity mismatch have been for decades limiting their integration on Si in the form of thin film technology. The nanowire geometry brings new prospects in this direction by reducing the contact area between mismatched materials,. Now, while growth of defect-free III-V structures on silicon is important, use in applications requires the nanostructures to be placed deterministically following a certain design/order. In this thesis we have studied different mechanisms to obtain ordered nanostructures on a silicon substrate, with the goal of increasing its functionality. The core part of this work was dedicated to the integration of III-V nanowires on Si in the formof ordered arrays. We have considered both GaAs and InAs nanowires. This process has several requirements: substrate fabrication and the growth process should be CMOS compatible, nanowires within the arrays should be grown vertically with a yield close to 100% and nanowires should be clones-looking and performing the same. An additional point to consider is that the fabrication process should be compatible with large scale techniques. The substrate requirements for obtaining ordered arrays of Ga-assisted GaAs nanowires on silicon were identified. In particular, we focused on the initial stages of growth, that turned to be key for achieving a high yield in the arrays. We found that the positioning of the Ga droplet within the predefined holes on the substrate determined whether the nanowire would grow perpendicularly to the substrate. Our HRTEMstudies on the titled nanowires show that the initial nanowire seeds seem to nucleate at the corner of the nanoscale holes. Instead, the crystal seeds of vertical nanowires occupy homogeneously the nanoscale holes. Achieving high yield in the growth of GaAs arrays on silicon also allowed us to study their evolution in time. We demonstrated that there is an incubation time for nanowires to start growing. This incubation time is different from NW to NWand leads to a relatively broad length distribution. We proposed a solution and showed how an increase in the supersaturation in the Ga droplet leads to the formation of homogeneous arrays. Growth of InAs nanowires in ordered arrays on silicon was based on the concept of guided growth. We used a SiO2 nanotube templates to promote vertical growth. Due to the directionality of MBE, achieving growth inside a nanotube was especially challenging. Our results provided new insights on the role of different pathways of the In and As4 adatoms during growth. In this part, large scale patterning by phase shift photolithography was demonstrated as an alternative to the conventionally used electron beam lithography. Stain etching method for producing porous silicon was applied on top-bottom fabricated Si micropillars. This led to geometrically driven electrochemical dissolution of silicon trough the center of the microstructure forming microtubes. The optical properties were also studied and used to produce functional 3D LED.

EPFL2017

Design and fabrication of suspended-gate MOSFETs for MEMS resonator, switch and memory applications

Nicolas Abelé

Wireless communication systems and handset devices are showing a rapid growth in consumer and military applications. Applications using wireless communication standards such as personal connectivity devices (Bluetooth), mobile systems (GSM, UMTS, WCDMA) and wireless sensor network are the opportunities and challenges for the semi-conductor industry. The trend towards size and weight reduction, low power consumption and increased functionalities induces major technological issues. Today, the wireless circuit size is limited by the use of lots of external or "off-chip" components. Among them, quartz crystal, used as the time reference in any wireless systems, is the bottleneck of the miniaturization. Microelectromechanical systems (MEMS) is an emerging technology which has the capability of replacing the quartz. Based on similar technology than the Integrated Circuit (IC), MEMS are referred as electrostatically, thermally or piezoelectrically actuated mechanical structures. In this thesis, a new MEMS device based on the hybridization of a mechanical vibrating structure and a solid-sate MOS transistor has been developed. The Resonant Suspended-Gate MOSFET (RSG-MOSFET) device combines both advantages of a high mechanical quality factor and the transistor intrinsic gain. The physical mechanisms behind the actuation and the behavior of this device were deeply investigated and a quasi-static model was developed and validated, based on measured characteristics. Furthermore, the dynamic model of the RSG-MOSFET was created, taking into account the non-linear mechanical vibrations of the gate and the EKV model, used for MOSFET modeling. Two fabrication processes were successfully developed to demonstrate the proof of concept of such a device and to optimize the performances respectively. Aluminum-silicon (Al-Si1%) and pure silicon-based RSG-MOSFETs were successfully fabricated. DC and AC characterizations on both devices enabled to understand, extract and evaluate the mechanical and MOSFET effects. A specifically developed RF characterization methodology was used to measure the linear and non-linear behaviors of the resonator and to evaluate the influence of each polarization voltages on the signal response. RSG-MOSFET with resonant frequencies ranging from 5MHz to 90MHz and quality factor up to 1200 were measured. Since MEMS resonator quality factor is strongly degraded by air damping, a 0-level thin film vacuum packaging (10-7 mBar) process was developed, compatible with both AlSi-based and silicon-based RSG-MOSFET. The technology has the unique advantage of being done on already released structure and the room temperature process makes it suitable for above-IC integration. In parallel, a front-end compatible process was defined and major build blocks were developed in industrial environment at STMicroelectronics. This technology is based on the Silicon-On-Nothing technology, originally developed for advanced transistor, and therefore making the MEMS resonator process compatible with CMOS co-integration. DC characterizations of SG-MOSFET had shown interesting performances of this device for current switch and memory applications. Mechanical contact of the gate with the MOSFET channel induces a current switching slope greater than 0.8mV/decade, much better than the theoretical MOSFET limit of 60mV/decade. Maximum switch isolations of -37dB at 2 GHz and -27dB at 10GHz were measured on these devices. A novel MEMS-memory has been demonstrated, based on the direct charge injection to the storage media by the mechanical contact of the metal gate. Charge injection and retention mechanisms were investigated based on measured devices. Cycling study of up to 105 cycles were performed without noticing major degradations of the electrical behavior neither mechanical fatigue of the suspended gate. The measured retention time places this memory in between the DRAM and the FLASH memories. A scaling study has shown integration and compatibilities capabilities with existing CMOS.

EPFL2007

Nanogap MEM resonators on SOI

Nicoleta-Diana Ciressan

Today's consumer electronics based on a large variety of time-keeping and frequency reference applications is based on quartz-crystal oscillators, because of their excellent performances in terms of quality factor, thermal and frequency stability. However, macroscopic size and CMOS incompatibility of quartz-crystal resonators draw a major limit on the miniaturization of wireless communication applications. For this reason, silicon microelectromechanical (MEM) resonators are considered promising candidates to replace quartz-oscillators in VLSI communication systems, due to their compactness, design flexibility and CMOS process compatibility. This work reports on the design, fabrication and characterization of MEM bulk lateral resonators with resonance frequencies in the order of tens of MHz. The need of stable, low cost and high yield processes for fabricating devices with extremely narrow (sub 100 nm) transduction gaps is a main research driver, together with the requirements of improved designs which include high quality factors and appropriate power handling. We are investigating two major designs: (1) longitudinal beam resonators and (2) novel fragmented-membrane resonators that respond to both high quality factor (Q) and low motional resistance (Rm) requirements. We propose several design optimizations for solving some of the issues which currently affect the MEM resonator performance, like the frequency stability and Q enhancement through energy loss minimization. An original fabrication process is presented, which enables the manufacturing of SOI-based, fully monocrystalline devices with 100 nm transduction gaps and aspect ratios as high as [60:1], without the need of advanced lithography techniques. We successfully validate the fabrication process on two different SOI substrates, with silicon film thicknesses of 1.5 µm and 6.25 µm. This thickness range combined to the doping level corresponds to partially depleted SOI, which can be a substrate of choice for the fabrication of future integrated hybrid MEMS-CMOS integrated circuits for communication applications. The fabricated structures are successfully characterized, demonstrating excellent resonator performance at room temperature. Q's as high as 235'000 and Rm's as low as 59 kΩ have been extracted in vacuum. Atmospheric pressure frequency response measurements of the fragmented membrane resonators show Q's of 3'600. This value is among the best reported to date, opening the possibility for atmospheric pressure applications such as mass-detection for gas sensing applications with detection done without a special package, just by direct exposure of the resonator to the environment. A novel study on temperature dependence (between 80 K and 320 K) of the fragmented membrane resonators is presented and discussed. Significant Q increase and Rm reduction are experimentally observed at cryogenic temperatures. The bulk mode resonators developed and discussed in this thesis can successfully be integrated in oscillator circuits, as we demonstrate by simulating a Pierce topology based on the calibrated equivalent circuit model of a 24.48 MHz fragmented membrane BLR. Our oscillator shows very good phase-noise performance of -142 dBc/Hz at 1 kHz offset from the carrier and the noise floor at -144 dBc/Hz, which nearly meets the GSM specifications.

EPFL2009