Multigate device | EPFL Graph Search

A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a metal–oxide–semiconductor field-effect transistor (MOSFET) that has more than one gate on a single transistor. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor (MIGFET). The most widely used multi-gate devices are the FinFET (fin field-effect transistor) and the GAAFET (gate-all-around field-effect transistor), which are non-planar transistors, or 3D transistors. Multi-gate transistors are one of the several strategies being developed by MOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's law (in its narrow, specific version concerning density scaling, exclusi

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device performance. As the density of number of devices increases a rise in dynamic and especially static power dissipation is ever more present, making this the biggest issue in microelectronics today. Planar silicon devices are therefore already being replaced by multiple-gate architectures and will be replaced by new channel materials and new switching mechanisms during the next 10 years. A means to decrease the threshold and supply voltage and, therefore minimizing power dissipation, is to employ devices which exhibit a steeper slope than the MOSFET limit of 60 mV/dec at room temperature. The Tunnel FET promises steep turn-on characteristics and low leakage currents as compared to MOSFETs which make it attractive for low-power operation. A great deal of work over the past years has been done to boost device performance of Tunnel FETs by combining ultimate wrap-gate architectures, incorporation of III/V materials and band engineering for hetero-tunnel junctions. The latter is seen as an ideal route towards achieving high drive currents and steep sub-threshold slopes at low supply voltages. This thesis investigates both Si Tunnel FETs and the route towards heterostructure Tunnel FETs, but also the technological challenges to achieve these device structures. The first part of this work deals with vapor-liquid-solid grown silicon in-situ doped n+-i-p nanowire Tunnel FETs in a lateral geometry, where the influence of the gate dielectric, i.e., SiO2 or HfO2, on device performance is investigated along with the study of low-temperature behavior. The devices having the strongest gate coupling due to the high-κ gate oxide HfO2 are shown to exhibit the best device performance as compared with the SiO2 gate stack. A vertical process for Si FETs is developed and improved to obtain a fully wrap-gate geometry. It is adaptable to different material systems and is the basis for the ongoing work on InAs-on-Si nanowire Tunnel FETs. Improved performance for these heterostructure devices requires in particular high doping concentrations as well as abrupt doping profiles to achieve high tunnel currents. Therefore, the second part focuses on the InAs material system and specifically the study of dopant incorporation. Doping is done in-situ using different precursors during growth. The InAs nanowires are grown in SiO2 mask openings on 〈111〉 Si substrates in a metal-organic vapor phase epitaxy process. The effect of the dopants and growth parameters on radial and vertical growth rates, wire morphology and resistivity is investigated. A method utilizing the measured Seebeck coefficient of the InAs nanowires to extract doping densities without the need of assuming a mobility value is presented. Two other reference methods where I-V characteristics of homo-and heterojunction InAs tunnel diodes are fitted by TCAD simulations confirm this approach. Doping densities ranging from 1·1017 cm−3 to 7.1·1019 cm−3 were achieved which is comparable to the highest doping concentration reported in bulk InAs. Furthermore, single vertical pn+-junctions are fabricated by growing n-type InAs nanowires on p-type InAs substrates, which show high tunnel current densities of 500 kA/cm2 at 0.3 V reverse bias. In the forward direction, negative differential resistance is obtained below 200 K, which is the characteristic feature of an Esaki diode.

EPFL2012

Electronic transport properties of vertical and lateral graphene-based heterostructures

Roberto Urcuyo Solorzano

Graphene has some drawbacks, like the absence of an electronic band gap which leads to only small gate switching ratios, and its fast carrier recombination that limits its use in optoelectronics. In order to overcome these issues, the aim of this thesis was to tune the properties of graphene by two different modification approaches. The first approach involved chemical functionalization to create lateral graphene heterostructures, whereas the second approach was directed toward vertical heterostructures that combine graphene with another 2D material. For the former case, two novel chemical functionalization methods were investigated. The first method relied upon hyperthermal molecular ion collisions with 4,4¿-azobis(pyridine). This enabled the covalent functionalization of graphene with a functionalization degree of up to 3%, as demonstrated by Raman in combination with XPS. AFM studies revealed that the functionalized sheets retain their topographic integrity. Thus obtained stripe-like patterns of covalently graphene within extended graphene sheets enabled enhanced on/off ratios upon gate switching. In the second functionalization, OsO4 was used to selectively introduce hydroxyl groups to graphene. Best results were obtained using UV light activation, which yielded graphene of high covalent functionalization degree, as concluded from its optical transparency and gate-induced on/off switching ratios of up to 500. Temperature dependent electrical measurements revealed 2D hopping as the dominant transport mechanism. The first type of vertical heterostructure, gr-TiOx-Ti diodes were fabricated and their electrical properties in the dark and under visible light illumination studied. In contrast to conventional MIM diodes, the performance of the graphene-based diodes was found to increase with decreasing thickness of the oxide insulator. Bias-induced modulation of the work function of graphene was identified as the key to the operation mechanism of the graphene diodes, enabling them to reach a very high asymmetry and nonlinearity (9000 and 8). The diodes compete well with state-of-the-art MIM diodes. Furthermore, the graphene-TiOx-Ti diodes could be operated as photovoltaic cell, with a maximum open-circuit voltage of 0.3 V and a short-circuit photocurrent of 14 nA under global illuminationt. This finding constitutes the first proof-of-principle of hot carrier extraction from graphene, based on the photovoltaic effect. The second type of vertical heterostructures was based on black phosphorus (BP). As a first step, thin BP sheets were combined with n-GaAs into novel pn devices. They displayed pronounced rectification behavior that, in the low bias regime, approaches that of ideal diodes. Moreover, when operated as photodiodes they reached external quantum efficiencies (EQE) above 30% under higher reverse bias. On this basis, the bP was then combined with gr into a p+/p heterojunction. Thus obtained devices achieved a maximum internal quantum efficiency (IQE) and responsivity of 13% and 10.7 mA/W, respectively. This IQE is the highest thus far reported for diodes comprising BP and another 2D material. Moreover, with the aid of a top gate it was possible to modulate both, the photo-conversion efficiency and photocurrent generation mechanism of the black phosphorous-graphene diodes. Together with the possibility to tune the photocurrent response by the thickness of the black phosphorous, these diodes emerge as promising photodetectors.

EPFL2016

LiNiO Junction Gate for High-performance Enhancement-mode GaN Power Transistor

Taifang Wang

GaN metal-oxide-semiconductor high electron mobility transistors (MOS)HEMTs) offer outstanding properties for next-generation power electronics devices. The high conductivity, high voltage blocking capability, high operation frequency, and device-level integration can be achieved on the same tech-nology platform. Moreover, the development of large-scale GaN-on-Si substrate reduces the cost of GaN lateral devices. That GaN power device has already been widely used in today's consumer electronics, and communications base stations with its superiority of power density, and energy efficiency.Despite the ideal side of GaN material for power transistor, the junction less structure of HEMT made it hard to achieve enhancement-mode (e-mode) operation. Existing solutions either rely on complicated processes or sacrifice device performance. A simple process, high performance, and reliable operation e-mode device are desired. This thesis proposes Li doped NiO as gate material combined with Tri-gate structure to achieve e-mode operation. This relied on a simple oxide deposition process, without using barrier recess or re-growth, and achieved a high-quality interface. These critical characteristics haven't been demonstrated on gate stack engineering for normally-off devices and reveal the outstanding stability of LiNiO as a junction gate.Moreover, to maximize the GaN power transistor performance boundary, a multi-channel junction gate device was developed, which uses multiple 2DEG channels to significantly reduce the device resistance while still operating at high breakdown voltage (VBR). The multi-channel junction gate de-vice presents state-of-the-art performance, stable operation, and simple process e-mode GaN transistor. Apart from achieving e-mode operation, the possibility of device-level integration was also explored. Reverse current conduction ability was achieved together with good on-state performance and voltage blocking capability. And the alternative method of regulating electric field to Tri-gate by grayscale lithography was developed. The results in this thesis reveal the great value of using oxide semiconductor LiNiO as junction gate, demonstrating high performance, e-mode, and reliable device, and unleashing the performance potential through multi-channel epitaxy.

EPFL2022