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This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4–5 GPa peak of lateral uniaxial tensile stress in the Si NW.
Mihai Adrian Ionescu, Matteo Cavalieri, Nicolò Oliva, Luca Capua
Jean-Michel Sallese, Farzan Jazaeri, Matthias Bucher
Elison de Nazareth Matioli, Pirouz Sohi, Jun Ma, Luca Nela, Catherine Erine, Minghua Zhu