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Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

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Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

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Insulation Coordination for a Modular Multilevel Converter Prototype

Design of an integrated thermoelectric generator power converter for ultra-low power and low voltage body energy harvesters aimed at ExG active electrodes

Design of an integrated thermoelectric generator power converter for ultra-low power and low voltage body energy harvesters aimed at ExG active electrodes

Design and Implementation of A Rail-to-Rail 460-kS/s 10-bit SAR ADC for the Power-Efficient Capacitance Measurement

A Low Power On-Chip Class-E Power Amplifier For Remotely Powered Implantable Sensor Systems

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

A 15 mu W 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB

T0003 / MilliNewton & CentoNewton force sensors / Deviation from ratiometric behaviour

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Design of an integrated thermoelectric generator power converter for ultra-low power and low voltage body energy harvesters aimed at ExG active electrodes

Design of an integrated thermoelectric generator power converter for ultra-low power and low voltage body energy harvesters aimed at ExG active electrodes

Insulation Coordination for a Modular Multilevel Converter Prototype

A Low Power On-Chip Class-E Power Amplifier For Remotely Powered Implantable Sensor Systems

Design and Implementation of A Rail-to-Rail 460-kS/s 10-bit SAR ADC for the Power-Efficient Capacitance Measurement

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

T0003 / MilliNewton & CentoNewton force sensors / Deviation from ratiometric behaviour

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

A 15 mu W 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB