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3.5-D Integration: A Case Study

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3.5-D Integration: A Case Study

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Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Memory Systems and Interconnects for Scale-Out Servers

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Parallel vs. Serial Inter-plane communication using TSVs

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication