Publication

Controllable polarity fet based arithmetic and differential logic

, ,
2014
Patent

Abstract

A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=AB+BC+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.

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Controllable polarity fet based arithmetic and differential logic

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