Inverter (logic gate)

Summary

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. It outputs a bit opposite of the bit that is put into it. The bits are typically implemented as two differing voltage levels. Description The NOT gate outputs a zero when given a one, and a one when given a zero. Hence, it inverts its inputs. Colloquially, this inversion of bits is called "flipping" bits. As with all binary logic gates, other pairs of symbols such as true and false, or high and low may be used in lieu of one and zero. It is equivalent to the logical negation operator (¬) in mathematical logic. Because it has only one input, it is a unary operation and has the simplest type of truth table. It is also called the complement gate because it produces the ones' complement of a binary number, swapping 0s and 1s. The NOT gate is one of three basic logic gates from which any Boolean circuit may be built up. Together with the AND gate and the OR gate, any function in bi

Official source

https://en.wikipedia.org/wiki/Inverter_(logic_gate)

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Related publications (11)

Related publications

Related people (2)

Related people

Related units (2)

Related units

Related concepts (20)

Related concepts

Related courses (9)

Related courses

Related lectures (30)

Related lectures

Related publications (11)

Triboelectric‐TFT Flip‐Flop for Bistable Latching of Dielectric Elastomer Actuators

Danick Briand, Rubaiyet Iftekharul Haque, Ronan Julien Hinchet, Xiaobin Ji, Alexis Pierre Henri Marette, Herbert Shea

A high‐voltage flip‐flop combining two self‐powered soft sensors with a flexible high‐voltage thin film transistor (HVTFT) is reported, and is used to electrically latch dielectric elastomer actuators (DEAs) in zero and high‐strain states. Two touch‐actuated triboelectric generators (TENGs) provide the gate input for the HVTFT that drives a DEA. One TENG is of positive polarity, while the other is of negative polarity, thus generating voltages either higher (100 V) or lower (−6 V) than the HVTFT threshold voltage. Used in a high‐voltage inverter configuration, there are two stable output voltage states, here 650 V (the “reset” state) and 50 V (the “set” state). The DEA is thus latched in one of two states, at 17.5% and 0% strain. The 650 V output is stable in time, while the 50 V state drifts up to 350 V after 10 s. Due to the highly nonlinear strain–voltage curve of the DEA, the drift of the output voltage in the “set” state leads only to a 2% increase of the DEA actuation strain in 10 s. By enabling bistable control of DEAs with TENGs, the TENG‐HVTFT latch paves the way toward soft robots with flexible embedded control circuitry.

2019

Submicrometer Organic Thin-Film Transistors: Technology Assessment Through Noise Margin Analysis of Inverters

Christian Enz, Rolando Ferrini, Nenad Marjanovic, Franz Xaver Pengg, Jean-Michel Sallese, Frédéric Zanella

In this paper, we propose a methodology to evaluate the potential of submicrometer organic thin-film transistors (OTFTs) with nanoimprinted gate and self-aligned source and drain contacts. In the first step, the dedicated static model we previously reported is updated to account for the subthreshold regime and is used to simulate a zero-VGS inverter (one of the most basic unipolar logic gate). Based on the extracted noise margins, two methodologies were studied to assess the potential of this technology in terms of p-logic digital circuits. The first one is De Vusser's VT-based method that we adapted to our OTFT model. The second one relies on statistical modeling and takes into account the actual worst case scenario for an inverter in terms of noise margins. It better represents the experimental distribution because of specific corner models. The different analysis studied in this paper shows that these OTFTs, in the current state of the technology, are still not ready for complex digital circuits as the throughput is expected to be quite low. In addition, the proposed methodology and related interpretation are technology-independent therefore this analysis may serve as a basis to characterize unipolar-logic printed electronics and can be further extended to complementary-logic circuits.

Institute of Electrical and Electronics Engineers2014

, , ,

This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching (3-10 mV/dec.) as well as hysteresis in both

I_D(V_{DS})

and

I_D(V_{GS})

. An inverter gain as high as -80 and a 300 mV hysteresis width in the transfer characteristics are reported at room temperature. Temperature stability of the devices up to 125degC and operation for more than

10^4

cycles without significant degradation are demonstrated, much beyond the performances of previously reported I-MOS device.

2008

, , ,

I_D(V_{DS})

and

I_D(V_{GS})

10^4

cycles without significant degradation are demonstrated, much beyond the performances of previously reported I-MOS device.

2008