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A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology, 2017 IEEE International Electron Devices Meeting (IEDM)

Related publications (32)

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Transconductance efficiency (g(m)/I-D) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of g(m)/I-D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully deple ...

2018

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This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear ons ...

Institute of Electrical and Electronics Engineers2017

Avalanche Microwave Noise Sources in Commercial 90-nm CMOS Technology

Christian Enz, Pierre-André Farine, Cyril Botteron, Gabriele Tasselli

This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different juncti ...

Institute of Electrical and Electronics Engineers2016

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Scott Anthony Lindner

The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus ...

Ieee2016

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Michele De Marchi, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack, Marios Barlas

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

Institute of Electrical and Electronics Engineers2016

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

Alexandre Schmid, Seyed Armin Tajalli, Mahsa Shoaran, Yusuf Leblebici

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

2015

A 2.4-GHz low power polar transmitter for wireless body area network applications

Christian Enz, Vladimir Kopta, Franz Xaver Pengg

A 2.4 GHz low power polar transmitter is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used as a direct digital-to-RF envelope converter. It effectively linearizes the input-output characteristic of the over ...

Springer Verlag2014

A Geiger Mode APD fabricated in Standard 65nm CMOS Technology

Edoardo Charbon, Hyungjune Yoon

We present the first avalanche photodiode (APD) successfully fabricated in standard 65nm CMOS technology. The APD operates both in proportional and Geiger mode at -60C to +60C temperature range. The device comprises an octagonal n+p-well junction surrounde ...

2013

Single-layer MoS₂

Branimir Radisavljevic

This thesis explores the electronic properties of one layered transition-metal dichalcogenide – single-layer MoS2, and demonstrates the first transistors and integrated circuits with characteristics that outperform graphene electronics in many aspects and ...

EPFL2013

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A 2.4-GHz low power polar transmitter architecture is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used to linearize the input-output characteristic of the overdriven class-C power amplifier. A model of the ...

2013