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Energy Efficient Sensing using Steep Slope Devices

Related publications (43)

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Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS, 2016 IEEE SENSORS

Edoardo Charbon, Harald Arjan Robert Homulle, Fabio Sebastiano

This paper presents the cryogenic characterization of the bipolar substrate PNPs that are typically employed as sensing elements in CMOS integrated temperature sensors. PNPs realized in a standard 160-nm CMOS technology were characterized over the temperat ...

2017

A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference

Kyojin Choo

This work presents a start-up boosting circuit designed for fast stabilization of a 2-transistor voltage reference. A clock injection method is used to induce a large bias on the 2-transistor voltage reference resulting in a fast output voltage settling wh ...

IEEE2017

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. W ...

EPFL2016

Organic thin-film transistors (TFTs) have undergone tremendous progress in the past few years. Their great potential in terms of mechanical flexibility, light weight, low-cost and large-area fabrication makes them promising candidates for novel electronic ...

EPFL2016

Cmos image sensor

Assim Boukhayma, Arnaud Peizerat

A CMOS image sensor including a pixel including: a photodiode in series with a MOS transistor between a first reference potential and a sense node; a MOS transistor connecting the sense node to a second reference potential; and a third MOS transistor assem ...

2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Analysis of Substrate Currents Propagation in HVCMOS technology

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi ...

IEEE2016

Traditional metal-oxide-semiconductor field effect transistor scaling has advanced successfully over 50 years providing significant increases in transistor count per chip and operating frequency, thus enabled the built of ever more performant and complex s ...

EPFL2015

Single-layer MoS₂

Branimir Radisavljevic

This thesis explores the electronic properties of one layered transition-metal dichalcogenide – single-layer MoS2, and demonstrates the first transistors and integrated circuits with characteristics that outperform graphene electronics in many aspects and ...

EPFL2013

FinFET integrated low-power circuits for enhanced sensing applications

Mihai Adrian Ionescu, Antonios Bazigos, Alexandru Rusu, Sara Rigante, Paolo Livi

This work presents different circuit architectures that combine sensing and signal readout functions. The basic building block is a Fin Field-Effect Transistor (Fin-FET) used as both sensor and metal gate transistor. Moreover, a hybrid partially gated FinF ...

Elsevier2013