Concept

Semiconductor memory

Publications associées (414)

Large-scale neural networks implemented with nonvolatile memory as the synaptic weight element: comparative performance analysis (accuracy, speed, and power)

Yusuf Leblebici, Irem Boybat Kara, Severin Sidler, Carmelo Di Nolfo

We review our work towards achieving competitive performance (classification accuracies) for on chip machine learning (ML) of large scale artificial neural networks (ANN) using Non-Volatile Memory (NVM) based synapses, despite the inherent random and deter ...

2015

Fault Tolerant Chip-to-Chip Communication with Advanced Voltage Regulator

Mohammad Amin Shokrollahi

Systems and circuits are described for transmitting data over physical channels to provide a fault tolerant, high speed, low latency interface such as between a memory controller and memory devices. Communications signals are communicated over interconnect ...

2015

Sort vs. Hash Join Revisited for Near-Memory Execution

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Nooshin Sadat Mirzadeh

Data movement between memory and CPU is a well-known energy bottleneck for analytics. Near-Memory Processing (NMP) is a promising approach for eliminating this bottleneck by shifting the bulk of the computation toward memory arrays in emerging stacked DRAM ...

2015

Sort vs. Hash Join Revisited for Near-Memory Execution

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Nooshin Sadat Mirzadeh

2015

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

Alexandre Schmid, Yusuf Leblebici, Abdulkadir Akin, Halima Najibi, Luis Manuel Gaemperle

Real-time disparity estimation requires real-time rectification which involves solving the models of lens distortions, image translations and rotations. Low complexity look-up-table based rectification algorithms usually require an external memory to store ...

Springer-Verlag Berlin2015

Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Georgios Karakonstantis, Andrea Bonetti

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated w ...

2015

Exploiting NVM in Large-scale Graph Analytics

Willy Zwaenepoel, Jasmina Malicevic

Data center applications like graph analytics require servers with ever larger memory capacities. DRAM scaling, how- ever, is not able to match the increasing demands for ca- pacity. Emerging byte-addressable, non-volatile memory technologies (NVM) offer a ...

2015

Charge-transport properties of monolayer MoS2 at the interface with dielectric materials

Simone Bertolazzi

Two-dimensional (2D) semiconductors, consisting of single-sheets of layered transition metal dichalcogenides (TMD), are attracting enormous interest from both fundamental science and technology. Monolayer molybdenum disulfide (MoS2), a typical example from ...

EPFL2015

Methods and systems for chip-to-chip communication with reduced simultaneous switching noise

Mohammad Amin Shokrollahi

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output nois ...

2015

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen, Georgios Karakonstantis

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst- ...

2015

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