Publications associées à Signoff (electronic design automation)

A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power

This paper presents a new power-efficient and high-speed voltage level shifter. In the proposed structure, the existing contentions at the internal nodes are reduced using auxiliary transistors and feedback networks, leading to a significant reduction in t ...

IEEE2023

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Guilherme Migliato Marega

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

SiGe Time Resolving Pixel Detectors for High Energy Physics and Medical Imaging

Fulvio Martinelli

In the last years, sub-nanosecond time-resolved particle detectors have been object of research by many companies and institutes since they represent an efficient tool to improve the performance of detecting systems for various applications such as High En ...

EPFL2022

Opportunities and challenges of 2D materials in back-end-of-line interconnect scaling

Benjamin Aaron Helfrecht, Alejandro Strachan

As the challenges in continued scaling of the integrated circuit technology escalate every generation, there is an urgent need to find viable solutions for both the front-end-of-line (transistors) and the back-end-of-line (interconnects). For the interconn ...

AMER INST PHYSICS2020

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Paolo Ienne, Grace Zgheib, Stefan Nikolic

The idea of introducing dedicated, fast paths between certain FPGA elements in order to reduce delay is neither new nor particularly hard to come up with. What is less obvious, however, is how to put such paths to actual use. In this work, we propose an ef ...

IEEE2020

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

IEEE2018

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

Design Techniques for Ultra High Frequency Clock Generation in 28 nm FDSOI Technology

Hasene Gülperi Özsema

Twentieth century has been the golden age of semiconductor industry by achieving a high level of growth as a courtesy of developments in fabrication techniques and downscaling of the technology. Since the downscaling in current lithography technology is re ...

EPFL2017

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Adam Shmuel Teman

SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SR ...

IEEE2014