Publications associées à Memory cell (computing)

ShiDianNao: shifting vision processing closer to the sensor

Paolo Ienne, Robert Fasthuber, Zidong Du

In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency a ...

ACM2015

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Jury Sandrini, Somayyeh Rahimian Omam, Maxime Victor Thammasack

Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of ...

IEEE2015

Accurate Power Analysis for Near-Vt RRAM-based FPGA

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of ...

2015

Modeling Parasitic Vertical PNP in HVCMOS

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach ...

IEEE2015

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash

Paolo Ienne, David Novo Bruna, Xavier Jimenez

Hybrid flash storages combine a small Single-Level Cell (SLC) partition with a large Multilevel Cell (MLC) partition. Compared to MLC-only solutions, the SLC partition exploits fast and short local write updates, while the MLC part brings large capacity. O ...

Assoc Computing Machinery2015

Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?

Andras Kis, Simone Bertolazzi, Wei Cao

Conventional floating-gate (FG) transistors (made with Si/poly-Si) that form the building blocks of the widely employed nonvolatile flash memory technology face severe scaling challenges beyond the 12-nm node. In this paper, for the first time, a comprehen ...

Ieee-Inst Electrical Electronics Engineers Inc2014

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Davide Sacchetto, Yusuf Leblebici, Tugba Demirci

A non-volatile latch circuitry, comprising a Re RAM cell configured to store a final value of the non-volatile latch circuitry; a data selection circuitry configured to connect or disconnect a data input to a plus voltage node and a minus voltage node of t ...

2014

High Sum-Rate Three-Write and Nonbinary WOM Codes

Write-once memory (WOM) is a storage medium with memory elements, called cells, which can take on q levels. Each cell is initially in level 0 and can only increase its level. A t-write WOM code is a coding scheme, which allows one to store t messages to th ...

Institute of Electrical and Electronics Engineers2014

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Memory cell (computing)

Exploiting NVM in Large-scale Graph Analytics

ShiDianNao: shifting vision processing closer to the sensor

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

Accurate Power Analysis for Near-Vt RRAM-based FPGA

Modeling Parasitic Vertical PNP in HVCMOS

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash

Overview of the IFMIF test facility design in IFMIF/EVEDA phase

Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

High Sum-Rate Three-Write and Nonbinary WOM Codes

Graph Chatbot

Chattez avec Graph Search

ShiDianNao: shifting vision processing closer to the sensor

Overview of the IFMIF test facility design in IFMIF/EVEDA phase

High Sum-Rate Three-Write and Nonbinary WOM Codes

Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?

Exploiting NVM in Large-scale Graph Analytics

Modeling Parasitic Vertical PNP in HVCMOS

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

Accurate Power Analysis for Near-Vt RRAM-based FPGA

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials