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Concept

Architecture de von Neumann

L’architecture dite architecture de von Neumann est un modèle pour un ordinateur qui utilise une structure de stockage unique pour conserver à la fois les instructions et les données demandées ou produites par le calcul. De telles machines sont aussi connues sous le nom d’ordinateur à programme enregistré. La séparation entre le stockage et le processeur est implicite dans ce modèle. Origine Cette architecture est appelée ainsi en référence au mathématicien John von Neumann, qui a élaboré en juin 1945 dans le cadre du projet EDVAC la première description d’un ordinateur dont le programme est stocké dans sa mémoire. Alan Turing, John William Mauchly et John Eckert (pendant leurs travaux sur l’ENIAC) ont également utilisé ce concept ou une idée proche, et ce indépendamment de von Neumann. Herman Goldstine (un collègue de John von Neumann) fit circuler une description inachevée, intitulée « Première ébauche d'un rapport sur EDVAC », basée sur les travaux d'Eckert et Mauc

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Publications associées (31)

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Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate.

Michaël Yannick Juillard

Active Debris Removal missions consist of sending a satellite in space and removing one or more debris from their current orbit. A key challenge is to obtain information about the uncooperative target. By gathering the velocity, position, and rotation of the desired object, the satellite is able to plan its trajectory and define the sequence of approach. It requires the use of a variety of sensors with often a high data rate. For this task, a dedicated payload computer is envisioned with the responsibility of processing the information from the various rendezvous sensors. This component has the goal to provide meaningful information to the main satellite computer about the targeted debris. The focus of this work is on the data processing, the number of elements, and the electrical energy with constraints due to internal communication.First, an avionic testbench was built at the EPFL Space Center to assess early hardware and software architectures. The goal is to enable Hardware-In-the-Loop testing while developing the payload computer. A communication data bus has been implemented between the Platform and the Payload On-Board Computer. Emphasis was placed on the reliability of the high-level protocol and multiple concepts for improvement were analyzed.In a second phase, the testbench has been extended to support other data buses. The aim was to develop a reliable and efficient backup or fall-back data bus in case of failure in the main link. Four data buses have been tested with extensive analyses on their resilience to error and the efficiency of their data exchange.In parallel, extensive work has been performed to develop a simulation and optimization tool. Its goal is to support the design of payload avionic architectures for ADR missions by providing trade-offs and analyses. In the first iteration, a simulator has been created with instances of various high-level elements modeled.The second iteration introduced the additional dimension of optimization. It is trying to determine the best set of instruments and algorithms to use. With this capability, numerous analyses have been conducted on the influence of various parameters linked to the general optimizer behavior. It allows us to better understand the strength and limitations of the tool.The third step regarding the tool was to start its verification. The task has been to develop an Hardware-In-the-Loop architecture to compare its behavior with the results of the optimizer. The implementation of various mock-up algorithms enables the verification of their models in the tool. These analyses guarantee the feasibility of the outputted solution.The last part was dedicated to the creation and analysis of a realistic payload avionic architecture. The goal was to test the capability of the tool with hardware elements inspired by actual components. This work has shown the procedure to efficiently use the tool in the design phase of a mission.In conclusion, the work on the communication between the Payload and the Platform On-Board Computer has brought valuable lessons and experiences to the projects. They can now be used for the establishment of the high-level protocol into ClearSpace-1 flight software. In addition, the optimizer created allows tackling the design of complex payload avionic architecture where mass saving and processing resources are crucial. It is an essential point to develop a highly efficient payload computer for an Active Debris Removal satellite.

EPFL2022

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CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Jérémy Pierre Benoit Fouriaux, Michael Lee Hines, James Gonzalo King, Pramod Shivaji Kumbhar, Aleksandr Ovcharenko, Felix Schürmann

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations that individually measure in the millions of core hours. Supercomputer centers are transitioning to next generation architectures and the work accomplished per core hour for these simulations could be improved by an order of magnitude if NEURON was able to better utilize those new hardware capabilities. In order to adapt NEURON to evolving computer architectures, the compute engine of the NEURON simulator has been extracted and has been optimized as a library called CoreNEURON. This paper presents the design, implementation, and optimizations of CoreNEURON. We describe how CoreNEURON can be used as a library with NEURON and then compare performance of different network models on multiple architectures including IBM BlueGene/Q, Intel Skylake, Intel MIC and NVIDIA GPU. We show how CoreNEURON can simulate existing NEURON network models with 4-7x less memory usage and 2-7x less execution time while maintaining binary result compatibility with NEURON.

2019

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This paper presents a wearable sensor architecture for frequency-multiplexed electrical impedance tomography (EIT) and synchronous multilead electrocardiogram (ECG) data acquisition. The system is based on a novel electronic sensing architecture, called cooperative sensors, that significantly reduces the cabling complexity and enables flexible EIT stimulation and measurement patterns. The cooperative-sensor architecture was initially designed for ECG and has been extended for multichannel bioimpedance measurement. This approach allows for an adjustable EIT stimulation pattern via frequency-division multiplexing. This paper also shows a calibration procedure as well as EIT system noise performance assessment. Preliminary measurements on a healthy volunteer showed the ability of the wearable system to measure EIT data synchronously with multilead ECG. Ventilation-related and heartbeat-related EIT images were reconstructed, demonstrating the feasibility of the proposed architecture for non-invasive cardiovascular monitoring.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Chargement

Ordinateur

Un ordinateur est un système de traitement de l'information programmable tel que défini par Alan Turing et qui fonctionne par la lecture séquentielle d'un ensemble d'instructions, organisées en progr

Central processing unit

A central processing unit (CPU)—also called a central processor or main processor—is the most important processor in a given computer. Its electronic circuitry executes instructions of a computer pr

Programme informatique

Un programme informatique est un ensemble d'instructions et d’opérations destinées à être exécutées par un ordinateur.

Un programme source est un code écrit par un informaticien dans un langage de

MICRO-435: Quantum and nanocomputing

The course teaches non von-Neumann architectures. The first part of the course deals with quantum computing, sensing, and communications. The second focuses on field-coupled and conduction-based nanocomputing, in-memory and molecular computing, cellular automata, and spintronic computing.

PHYS-403: Computer simulation of physical systems I

The two main topics covered by this course are classical molecular dynamics and the Monte Carlo method.

CS-108: Practice of object-oriented programming

Les étudiants perfectionnent leurs connaissances en Java et les mettent en pratique en réalisant un projet de taille conséquente. Ils apprennent à utiliser et à mettre en œuvre les principaux types de collections (listes, ensembles, tables associatives), et examinent quelques patrons de conception.