Publications associées à Logique floue

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

New York2023

Technology Mapping Using Multi-output Library Cells

Giovanni De Micheli, Alessandro Tempia Calvino

Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. Even if technology libraries contain multi-output cells, state-of-the-art techniques fully exploit single-output cells only. Mul ...

2023

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Giovanni De Micheli, Andrea Costamagna

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

IEEE2022

Dynamic Probabilistic Pruning: A General Framework for Hardware-Constrained Pruning at Different Granularities

Alexandre Schmid, Lizeth Gonzalez Carabarin

Unstructured neural network pruning algorithms have achieved impressive compression ratios. However, the resulting-typically irregular-sparse matrices hamper efficient hardware implementations, leading to additional memory usage and complex control logic t ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Three-Input Gates for Logic Synthesis

Giovanni De Micheli, Mathias Soeken, Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Giovanni De Micheli, Heinz Riener, Shubham Rai, Akash Kumar

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

2021

An untethered mechanically-intelligent inchworm robot powered by a shape memory alloy oscillator

Yves Perriard, Paolo Germano, Thomas Guillaume Martinez, Sean Thomas

Shape Memory Alloy (SMA) based actuators have become ideal candidates for use in compact and lightweight applications. These smart materials have often been referred to as artificial muscles due to their high work volume density. In this paper, a flexure-b ...

2021

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa, Heinz Riener

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

2020

SAT-Sweeping Enhanced for Logic Synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa

SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification and synthesis appl ...

IEEE2020

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Logique floue

Improving Standard-Cell Design Flow using Factored Form Optimization

Technology Mapping Using Multi-output Library Cells

Glare analysis of an integral daylighting and lighting control strategy for offices

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Dynamic Probabilistic Pruning: A General Framework for Hardware-Constrained Pruning at Different Granularities

Three-Input Gates for Logic Synthesis

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

An untethered mechanically-intelligent inchworm robot powered by a shape memory alloy oscillator

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

SAT-Sweeping Enhanced for Logic Synthesis

Graph Chatbot

Chattez avec Graph Search

Technology Mapping Using Multi-output Library Cells

Improving Standard-Cell Design Flow using Factored Form Optimization

Dynamic Probabilistic Pruning: A General Framework for Hardware-Constrained Pruning at Different Granularities

Glare analysis of an integral daylighting and lighting control strategy for offices

An untethered mechanically-intelligent inchworm robot powered by a shape memory alloy oscillator

Three-Input Gates for Logic Synthesis

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

SAT-Sweeping Enhanced for Logic Synthesis

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks