Building Blocks for an Ultra Low-Power MEMS-based Radio

The recent advances made in MEMS and particularly in RF MEMS technology are enabling new architectures for the integration of RF transceivers with improved performance and smaller size. Several fundamental building blocks benefit from the availability of high-Q resonators in the RF front-end and the frequency synthesizer to lower power consumption, phase noise and die area. In addition, the compatibility of MEMS with CMOS opens the door to a higher integration level using for example an above-Q approach. This paper presents the recent work made at CSEM in the field of low-power transceiver for wireless sensor network applications. It first presents the high-Q resonators, including the BAW resonators used in the RF front-end and in the RF oscillator together with MEMS used in the low frequency reference oscillators. These MEMS are activated thanks to an AlN piezo layer avoiding the need for high voltage generation which is incompatible with the low-power and low-voltage requirement. These MEMS are also temperature compensated by the combination of additional layers and electronics means. The paper then focuses on the main building blocks that can take advantage of high-Q resonators. The fundamentals of oscillators built around high-Q devices is described, highlighting the basic trade-offs. It is also described how to take advantage of such devices within a receiver front-end.

Low-power and low-voltage analog baseband and quadrature frequency synthesizer

Uroschanit Yodprasit

Following the trend in portable wireless communications, this dissertation explores new approaches to designing of power-critical building blocks in the elementary circuit level. Specifically, the work focuses on designs of baseband continuous-time Gm-C filter, LC-resonator quadrature oscillators, transistor-only quadrature oscillators and LC-resonator frequency dividers. The established circuits share a common design objective of low-power and low-voltage operation, where the simplicity of the demonstrated topologies serves as a basis. The dissertation is separated in two parts. The first part is dedicated for the baseband section where a 3rd-order Bessel filter is designed and fabricated. The filter comprises a set of linear transconductors, which each one is based on the operation of triode-biased transistors. According to the operation in this region and to the simplicity of the transconductor, high dynamic range can be achieved for a supply voltage as low as 1.2 V. In the other part, attempts in reducing the power consumption of two critical building blocks in a frequency synthesizer, namely, the quadrature oscillator and the first-stage frequency divider, are introduced. For the oscillators, two quadrature oscillators based on LC resonators are presented, in conjunction with a transistor-only quadrature oscillator. Quadrature signal generations in these designs are achieved by making use of the principles of ring oscillator and coupled oscillator. The last building block that is designed in this part is the LC-based injection-locked frequency divider. The single-ended Colpitts oscillator topology is used as the core circuit of the divider due to its simplicity and low-voltage property. Detailed analysis concerning the phase relationship between the input and the output leads to the implementations of differential and quadrature divider configurations. Although a silicon integration is done only for the baseband filter, the concept, the operation and the theories developed for the quadrature oscillators and the frequency dividers have been verified against simulations and measurements employing low-frequency discrete prototypes. As they are illustrated in each chapter, the established theories match closely to the measurements.

EPFL2006

A low-power 2.4 GHz CMOS receiver using BAW resonators

Jérémie Chabloz

It has already been a few years since the first appearance of micro-electromechanical systems (MEMS) in academic research. Since then, a broad number of devices have been designed under this generic term. Bulk-acoustic wave (BAW) resonators are among the few of them which have become exploited at industrial level. They are mainly used to implement filters for mainstream telecommunication applications. In a different domain, potential applications for integrated wireless transceivers are flourishing. While some of them require always higher data rates, others need devices with low data rate but even lower power consumption. The goal of this thesis is to explore ways of using BAW resonators to implement building blocks for such a low-power radio and actually verify the postulate that this could help improving power consumption as well as miniaturize key functionalities. For the active integrated circuit part, the choice of a standard digital 0.18µm CMOS process established itself for its low cost and ubiquity. The specifications for the developed radio receiver are calculated for a physical layer derived from the well known Bluetooth communication protocol in the 2.4GHz ISM band with similar applications scenarii but with much lower data rates and wider channel spacing. After presenting the advantages and limitations of the devices, the implications for using BAWresonators to implement a low-power radio are investigated at circuit and system levels and a super-heterodyne architecture is proposed. A selective low-noise amplifier (LNA) is used at the circuit front-end to yield image and blocker rejection. Measurements for the RF front-end comprising an external balun, the selective LNA, a first downconversionmixer and an intermediate-frequency (IF) amplifier showed an overall noise figure of 11dB for a current consumption of 1.5mA under 1.2V. The high selectivity of the design yields an image rejection ratio of at least 50dB and allows to decrease linearity requirements and thus power consumption. A slightly improved version of the same front-end integrated together with the analog baseband signal processing chain but still using external local oscillators showed sensitivities of -96dBm at 100kbps symbol rate and -93dBm at 200kbps with an external state-of-the art FSK demodulator, allowing to extrapolate a global noise figure of 12.2dB for a global current consumption of 2.3mA under 1.2V. The proposed solution for the frequency synthesis uses both a BAW oscillator for the first downconversion to IF and a quadrature quasi-harmonic relaxation oscillator to translate the signals to baseband. The relaxation oscillator is embedded within a phase-locked loop (PLL) for which all the required blocks are discussed. Particularly, a novel modular multi-modulus frequency divider is presented, which does not necessitate complicated logic to yield the wanted division ratio and uses dynamic logic. The necessary digital circuitry to control the frequency generation is discussed as well. Finally, measurements for the complete receiver using the proposed frequency synthesis as well as digital control and demodulator implemented on FPGA are presented.

EPFL2008

Low-power and low-voltage analog baseband and quadrature frequency synthesizer

Uroschanit Yodprasit

EPFL2006

A low-power 2.4 GHz CMOS receiver using BAW resonators

Jérémie Chabloz

EPFL2008