Publication
A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology
Publications associées (32)
Front-End Circuits for Radiation-Hard Monolithic CMOS Sensors targeting High-Energy Physics Applications
Monolithic pixel sensors integrate the sensor matrix and readout in the same silicon die, and therefore present several advantages over the more largely used hybrid detectors in high-energy physics. They offer an easier detector assembly, lower cost, lower ...
EPFL2023An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS
We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...
IEEE2022Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments
DC-DC converters based on Application Specific Integrated Circuits (ASICs) have been developed in this doctoral work for the High-Luminosity Large Hadron Collider (HL-LHC) experiments at CERN. They step down the voltage from a 2.5 V line and supply a load ...
EPFL2020Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology
David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Mohamed Mostafa Sabry Aly, Halima Najibi
Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...
2020Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics
The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâs la ...
EPFL2019Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization
Elmira Shahrabi, Yusuf Leblebici, Tugba Demirci
The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...
ELSEVIER SCIENCE BV2019ReRAM From Material Study to CMOS Co-integration
The revolution of information-technology owes to silicon-based complementary-metal-oxide (CMOS) technology. However, CMOS technology approaches its physical limitation hardening the further progress of memory devices as well as computing paradigm requiring ...
EPFL2019Modeling of Total Ionizing Dose Degradation on 180-nm n-MOSFETs Using BSIM3
Nergiz Sahin Solmaz, Mustafa Berke Yelten, Sadik Ilik
This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal-oxide-semiconductor field-effect transist ...
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019Three-Dimensional Nano-Acoustic Bragg Reflectors for CMOS Embedded NEMS
Luis Guillermo Villanueva Torrijo, David Ruffieux, Soumya Yandrapalli
Integration of CMOS electronic circuits and electromechanical resonators has been pursued for a long time by many different research groups and even foundries. This would improve the overall performance of electromechanical oscillators and sensors. However ...
Institute of Electrical and Electronics Engineers2017