Highly sensitive vertical hall sensors in CMOS technology

Vertical Hall sensors are capable of measuring surface-parallel components of the magnetic field. They allow therefore relatively easy conception of single-chip multi-axial magnetic sensors compared to solutions using horizontal Hall plates. The modern trend in the field of Hall sensors is to integrate them into electronic circuitry for signal processing. Before this thesis, highly sensitive vertical Hall sensors completely compatible to a technology adequate for co-integration of electronic circuitry were not available. This is the reason why we present in this thesis the developed knowledge that is necessary for the design and manufacture of highly sensitive vertical Hall sensors in CMOS technology. We first present the principles of the technology choice. A wide selection of CMOS processes is presently available, but in order to obtain optimal sensitivity we have to choose "the right" one. The performances can vary easily by 50% from one technology to another. The best choice are CMOS high-voltage technologies since they deliver n-diffusion layers with relatively low doping level and deep junction depth. We present a novel layout of vertical Hall sensors that has six contacts in the active sensor zone and is a development of the known layout that uses only four contacts. The additional contacts improve the sensitivity and reduce the systematic offset considerably. If we re-use layouts that were optimal for not-CMOS compatible technologies, we will see that the results are not satisfying. We have to develop our specific design parameters that are optimal for the chosen technology. The key for high sensitivities is the strong miniaturization of the devices down to technological limits given by the design rules, but sometimes even beyond that. Some of the design rules can be broken with benefit for the obtained sensor devices. In general, minimum contact sizes and contact distances are preferable as well as a minimum sensor thickness. The difficulty is however to find the absolute minimum before device degradation or even failure will occur. Our optimized sensors achieved voltage related sensitivities of about 0.04 V/(VT) and current related-sensitivities up to 400 V/(AT) that are comparable to existing CMOS compatible horizontal Hall plates. Such sensitivities were never reported for a standard CMOS process, without any additional pre- or post-processing steps. The miniaturization of the Hall devices has however also negative aspects e.g. an increase in sensor offset, noise and output non-linearity. Although Hall sensors have many advantages in comparison to other magnetic sensors (simple structure, low fabrication costs, very good linearity, robustness) they have the drawback of a big Abstract offset voltage that is often too big for many applications. This is why an enormous effort was made by researchers in the past to develop offset reduction methods for horizontal Hall plates. We state in this thesis that, in principle, the same techniques are applicable on vertical Hall sensors but for an optimal efficiency certain principles/parameters have to be respected. We reveal the relations of important parameters as the type of layout (number of sensor contacts), the use of single or coupled sensors, the type of spinning-current, bias level etc. In the optimal case we can obtain residual offset values lower than 200 μT for bias voltages up to 2 V. The spinning current method was originally developed for offset compensation, but it has other beneficial influences on the sensor output signal as well. It is capable to remove a large amount of flicker noise if the spinning is executes at adequately high clock frequencies. We show that the efficiency of flicker noise removal is dependent on the bias current through the sensor. We discovered another positive side effect of the spinning-current method: the elimination of the planar Hall effect. While the planar Hall sensitivity for our sensors is initially about 1% of the normal one at B = 2 T, we obtain with the compensation technique values of only 0.02%. After the presentation of general characteristics of the separate sensors, we present two microsystems based on the developed vertical Hall sensors. At first, we present a 2D magnetic microsystem which is well adapted for the construction of contactless angular encoders with a measurement range of 360°. We profit here especially from the very low offset (< 400 μT) obtained with the spinning current method, since offset is in general the main source of angular errors in such systems. Existing angular measurement systems need in general a special (offset) calibration of the sensor unit in order to achieve an accuracy of 2.5‰ full scale. We obtain such a precision directly with our system for a wide temperature range from -30 to 100 °C. With one specific sensor calibration for the compensation of residual offset, sensitivity mismatch and phase mismatch of the two axes, we attain a precision of about 0.5‰ FS over the same temperature range, a performance never before reported with a magnetic sensor system. The microsystem is therefore an excellent candidate for the majority of low-cost angular measurement applications. As a second example we presented the first fully CMOS integrated three-dimensional Hall probe, consisting of a combination of one Hall plate and four vertical Hall devices. The microsystem allows an application as a universal magnetic field probe in the wide field range from 0.1 mT to 20 T. The probe can be easily used for small volumes because of its small size and the fact that the signal processing circuitry already is directly integrated onto the chip. The precision as a 3D magnetometer is limited by the sensitivity mismatch of about 5% FS. The probe is an ideal candidate for low-cost teslameter applications with limited precision.

High Bandwidth CMOS Magnetic Sensors Based on the Miniaturized Circular Vertical Hall Device

Mirjana Banjevic

Hall-effect devices make up by far the largest part of all magnetic sensors on the market today. The main reason is compatibility of Hall devices with modern semiconductor technology. In particular, integrated Hall sensor micro-systems fabricated in low-cost complementary metal oxide technology (CMOS) have dominated the market of magnetic sensors over the last decade. Recently, a new Hall device – the circular vertical Hall device (CVHD) – joined the family of CMOS compatible Hall devices. The CVHD can be biased and Hall voltage retrieved from it such that its output is a sine wave signal. The amplitude of the sine wave signal contains the information on the magnitude of the magnetic field, while the phase of the sine wave signal carries the information on the direction of the magnetic field. This is why a CHVD can be thought of as the first Hall device measuring an in-plane magnetic induction vector. It is due to this feature that the CVHD was first used as a sensing device in magnetic angular sensors. These CVHDs had a large number of contacts leading to a high angular accuracy, but limiting bandwidth of the sensor. This thesis was devoted to exploring and pushing the limits of CVHDs and integrated magnetic sensors based on CVHDs. The first aim of the thesis was to study the limits of bandwidth increase while keeping satisfying accuracy of angular sensors based on the CVHD. In order to increase the angular sensor's bandwidth, we optimized the CVHD, the front end of the sensor comprising the device and interface electronics, and finally the system level topology. The CVHD was ultimately miniaturized to the device containing only eight contacts (8CVHD). The smaller the number of contacts, the faster is obtained the sine wave signal from the CVHD. A novel symmetric Hall voltage retrieval facilitated by the geometry and including all contacts was used. It led to the residual offset voltage comparable with devices having a much larger number of contacts. It was shown that the increase of the sensor's bandwidth is not only limited by the device but also by the interface electronics. This is particularly so because the sensor system relies on the spinning current method for offset reduction. In this case, the interface electronics includes spinning switches and a preamplifier. The spinning current method introduces voltage spikes that decrease accuracy when increasing bandwidth. The modeling of the horizontal Hall device and the interface electronics containing spinning switches and preamplifier was presented. The model was extended for the specific case of the sensors based on the 8CVHD. Three solutions to tackling the challenge of increasing the spinning frequency, or equivalently sensor's bandwidth, while maintaining accuracy were proposed and discussed. The first one is a novel solution relying on the high input capacitance of the preamplifier which together with the sensing switch on-resistance filters out the voltage spikes. The second solution examines the partial guard band to remove a part of the spikes' energy without compromising the high spinning frequency. The third solution is based on the cancellation of the voltage spikes by the time-shifted clockwise and counterclockwise spinning current method on two pairs of devices. These solutions were employed in three different sensors based on the 8CVHD. On the system level, a novel concept of the angular sensor based on two 8CVHDs was used. The outputs of the 8CVHDs are separately processed in two channels and they act as mutual reference signals. The Hall voltage retrieval is done in the clockwise direction for the first device, and in the counter clockwise direction for the second one. In this way there is no need for the reference signal as in the known concept. The use of two devices doubles the sensitivity of the sensor. Finally, the optimized device, the solutions for the design of interface electronics, and the system level topology were combined in two implementations in 0.35 µm CMOS technology. The first implementation employed one 8CVHD per channel. The average angular error was found to be ± 4° with the sensor's bandwidth of about 300 kHz. The second implementation employed an array of 8CVHDs per channel. The average angular error was found to be ± 1.5° with the sensor's bandwidth of about 500 kHz. The second aim of the thesis was to investigate the feasibility of magnetic sensors based on the 8CVHD for some challenging applications. To this end a two-dimensional (2D) magnetometer and a magnetic sensor for use in open-loop current transducer were designed and experimentally characterized. The novel system level concept for the 2D CMOS integrated magnetometer based on the 8CVHD was proposed. It enables common biasing, signal retrieval, dynamic cancellation of offset and low frequency noise, and front-end signal conditioning electronics for both components of the measured in-plane magnetic field vector. Separation of two channels is postponed to the point where signal levels are high and less susceptible to nonidealities and mismatches of signal conditioning electronics. The magnetometer features bandwidth around 60 kHz, wide dynamic range 0-1.5 T, high spatial resolution, and a high measurement resolution of 300 µT over frequency range 0-30 kHz. The magnetic sensor for the open-loop current transducer is based on the high bandwidth angular sensor and a tangent converter circuit. The initial experimental verification showed the bandwidth around 100 kHz, along with a wide dynamic range and good linearity.

EPFL2011

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.

EPFL2005

Offset compensation based on distributed Hall system architecture

Pavel Kejik, Radivoje Popovic

Integrated Hall devices have the great advantage, over other magnetic sensors, that they can be fully fabricated by a standard CMOS process. However they are known to have a relatively large offset (i.e. residual voltage at zero magnetic field). Techniques such as spinning current [1] or orthogonal coupling are effective to reduce this offset down to the 100 uT range. Still, in order to gain a real advantage over competing technologies [2], the offset of integrated Hall sensors should be reduced further, to the 10 uT range. The idea to achieve low offset performances is to reduce the sensor non-linearities. According to the reverse field reciprocity principle [3], the spinning current method completely cancels the offset in a linear system. It is now well understood that the major cause of non-linearity is either the junction field effect [4] or the carrier velocity saturation, depending on the device geometry. In both cases the non-linearity increases with the device bias voltage. However, reducing the bias voltage to reduce offset degrades the signal to noise ratio, since the noise depends mainly on device resistance. Therefore, the solution to maintain the signal-to-noise ratio is to integrate an array of Hall devices. This architecture allows finding a good trade-off between offset reduction, sensitivity, bandwidth, and current consumption. We have realized a system in 0.35 um CMOS standard technology to demonstrate the potential of this architecture. A primitive cell containing a Hall device, spinning current block and an amplification unit was designed in order to build an arbitrarily large array. This particular test system is built of 16 primitive cells, equally distributed over the layout. The Hall signal is processed in a differential way and can be demodulated using time continuous or switched capacitor technique, depending on required signal bandwidth. In addition, a switching scheme designed to reduce the problems of charge injection and the related switching spikes was implemented. Promising results are shown and the relation between parameters, such as the bias current, the number of cells, the layout distribution and the selected signal treatment technique, are discussed.

2010