Analysis of CMS noise reduction for 65 nm CIS

This work explores the combination of a downscaled technology with in-pixel source-follower (SF) optimization, a high column-level gain and an analog implementation of Correlated-Multiple-Sampling (CMS) for noise reduction of CIS readout chains. Transient noise simulations show that in the optimal condition of a pMOS SF, a column-level gain equal to 64 and a CMS of order 8, the noise can be reduced to the extremely low value of 0.20e-rms, with a readout time of 43 μs, demonstrating the possibility of true photoelectron counting for this standard 65 nm process.