Are you an EPFL student looking for a semester project?
Work with us on data science and visualisation projects, and deploy your project as an app on top of Graph Search.
This lecture covers the implementation of logic gates in semiconductor material, focusing on two main logic families: Transistor to Transistor Logic (TTL) and Complementary Metal Oxide Silicon (CMOS). It discusses the technology of Integrated Circuits (ICs), static and dynamic hazards, gated clocks, real D flip-flops, metastability, critical path, maximum clock frequency, and switch debouncing. The lecture also delves into the elimination of static hazards using Karnaugh maps, the theory of zero-delay models, and the construction of NOR gates in TTL and CMOS technologies.