Network on a chip

A network on a chip or network-on-chip (NoC ˌɛnˌoʊˈsiː or nɒk ) is a network-based communications subsystem on an integrated circuit ("microchip"), most typically between modules in a system on a chip (SoC). The modules on the IC are typically semiconductor IP cores schematizing various functions of the computer system, and are designed to be modular in the sense of network science. The network on chip is a router-based packet switching network between SoC modules. NoC technology applies the theory and methods of computer networking to on-chip communication and brings notable improvements over conventional bus and crossbar communication architectures. Networks-on-chip come in many network topologies, many of which are still experimental as of 2018. In 2000s researchers had started to propose a type of on-chip interconnection in the form of packet switching networks in order to address the scalability issues of bus-based design. Preceding researches proposed the design that rout

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A system on a chip or system-on-chip (SoC ,ˈɛsoʊsiː; pl. SoCs ,ˈɛsoʊsiːz) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components

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Quantitative Modelling and Comparison of Communication Schemes to Guarantee Quality-of-Service in Networks-on-Chip

Mehmet Harmanci, Paolo Ienne, Yusuf Leblebici

We address the quantitative comparison of two basic connection schemes for on-chip communication, connection-oriented and connection-less, regarding their enforcement of a defined Quality-of-Service for the communication. For such comparison, we have built similar models for the two approaches, whose simulation highlights the drawbacks and opportunities of each solution. We demonstrate that for variable bit-rate applications, the end-to-end delay for the individual flows is less stable in the connection-oriented scheme than in the connection-less scheme.

2005

A Predictable Communication Scheme for Embedded Multiprocessor Systems

Mehmet Harmanci, Paolo Ienne, Yusuf Leblebici

Networks-on-Chip are emerging as a widely accepted alternative for the traditional bus architectures. However, their applicability by the system designers is far away from being intuitive due to their lack of predictability. This communication predictability can be obtained statically or dynamically. A dynamic allocation is more suitable for flexible multiprocessor systems and requires the implementation of a Quality-of-Service (QoS) mechanism. This paper explores the main QoS schemes suitable for such systems: connection-oriented and connectionless. The simulation results show that the connectionless scheme provides a better predictability in terms of message latency with an acceptable buffer requirement. This work provides the designer with valuable guidelines to choose a priori the QoS parameters such that they can be confident on the predicted results.

2006

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Federico Angiolini, Luca Benini, Giovanni De Micheli, Srinivasan Murali, Dara Rahmati, Hamid Sarbazi-Azad

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst- case bandwidth and latency bounds for RT traffic streams on wormhole-switched NoCs with arbitrary topology. The proposed methods apply to best-effort NoC architectures, with no extra hardware dedicated to RT traffic support. By applying our methods to several realistic NoC designs, we show substantial improvements (more than 30% in bandwidth and 50% in latency, on average) in bound tightness with respect to existing approaches.

Institute of Electrical and Electronics Engineers2013

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