VHDL for SynthesisCovers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.
VHDL PackagesCovers the importance of VHDL packages in simplifying design consistency and minimizing errors in VHDL circuits.
Test of VLSI SystemsCovers test techniques for digital VLSI systems, including fault modeling and design for testability.
Storage Management in SmartDataLakeExplores storage management challenges in transitioning to data lakes, addressing software and hardware heterogeneity, unified storage design, and performance optimization.
Formally Verified Chisel DesignsExplores formally verifying Chisel designs using SMT solvers and covers examples like delayed assertions and proofs by induction.