Skip to main content
Graph
Search
fr
|
en
Login
Search
All
Categories
Concepts
Courses
Lectures
MOOCs
People
Practice
Publications
Startups
Units
Show all results for
Home
Lecture
Semicustom RTL Design: Frontend with Synthesis
Graph Chatbot
Related lectures (31)
Previous
Page 1 of 4
Next
Semicustom RTL Design: Design Flow and Standard Cells
Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.
Semicustom RTL Design: Backend
Explores the backend design flow in semicustom ASIC design, covering layout, clock tree generation, and tapeout preparation.
Hardware Description Languages
Explores the history and significance of Hardware Description Languages in automating design processes and describing parallel hardware.
How we design chips: The Digital VLSI Design Flow
Explores the principles and methodologies for designing integrated circuits, covering design flows, VLSI styles, abstraction levels, and the semiconductor ecosystem.
Logical Effort: Fundamentals of VLSI Design
Covers the Logical Effort method for optimizing logic delay and gate sizing impact.
Synchronous Digital Circuits: Principles and Design
Covers principles of synchronous RTL design, custom digital circuits, Y-Diagram visualization, signal classes, and hierarchy management.
Fundamentals of VLSI Design
Covers the fundamentals of VLSI design, focusing on circuit optimization and complex system composition.
Simulation-Based Verification
Explores simulation-based verification in VLSI systems using compiled-code and event-driven algorithms.
Introduction to Advanced VLSI Design
Covers Advanced VLSI Design concepts, including Full Custom Design and Parallel Prefix Adder.
Static Timing Analysis
Explores static timing analysis in digital system design, covering setup and hold time requirements, critical paths, and timing conditions.