Publications related to Double-Gate Pentacene TFTs with Improved Control in Subthreshold Region

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Mihai Adrian Ionescu, Kirsten Emilie Moselund, Clarissa Convertino

InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal-oxide-semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power ...

NATURE RESEARCH2021

P-GaN Tri-Gate MOS Structure for Normally-Off GaN Power Transistors

Elison de Nazareth Matioli, Pirouz Sohi, Jun Ma, Luca Nela, Catherine Erine, Minghua Zhu

In this letter, we present a new concept for normally-off AlGaN/GaN-on-Si MOS-HEMTs based on the combination of p-GaN, tri-gate and MOS structures to achieve high threshold voltage (V-TH) and low on-resistance (R-ON). The p-GaN is used to engineer the band ...

2021

Deep-UV-Enhanced Approach for Low-Temperature Solution Processing of IZO Transistors with High-k AlOx/YAlOx Dielectric

Danick Briand, Jaemin Kim, Alessio Mancinelli

Solution processing is an attractive alternative to standard vacuum fabrication techniques for the large-area manufacturing of metal oxide (MOx)-based electron devices. Here, we report on thin-film transistors (TFTs) based on a solution-processed indium zi ...

AMER CHEMICAL SOC2020

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Mihai Adrian Ionescu, Igor Stolichnov, Ali Saeidi, Teodor Rosca, Matteo Cavalieri

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by u ...

AMER CHEMICAL SOC2020

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Mihai Adrian Ionescu, Christian Enz, Igor Stolichnov, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

2019

Polarity Control of Top Gated Black Phosphorous FETs by Workfunction Engineering of Pre-Patterned Au and Ag Embedded Electrodes

Mihai Adrian Ionescu, Igor Stolichnov, Wolfgang Amadeus Vitale, Emanuele Andrea Casu, Nicolò Oliva

We propose and experimentally demonstrate top-gated complementary n- and p-type black phosphorous field effect devices (FETs) by engineering the workfunction of pre-patterned electrodes embedded in a SiO2 bottom layer. Pre-patterned electrodes offer the ad ...

2018

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Christian Enz, Farzan Jazaeri, Chunmin Zhang, Federico Faccio

This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of nMOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual nMOSFETs of various siz ...

2018

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

Mihai Adrian Ionescu, Cem Alper, Arnab Biswas, Florin Udrea

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear ons ...

Institute of Electrical and Electronics Engineers2017

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Mihai Adrian Ionescu, Anna Krammer, Teodor Rosca, Josef Andreas Schuler, Wolfgang Amadeus Vitale, Cem Alper, Arnab Biswas, Emanuele Andrea Casu, Qun Zhao

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursu ...

Nature Publishing Group2017

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Double-Gate Pentacene TFTs with Improved Control in Subthreshold Region

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Characterization and Modeling of Total Ionizing Dose Effects on Nanoscale MOSFETs for Particle Physics Experiments

P-GaN Tri-Gate MOS Structure for Normally-Off GaN Power Transistors

Deep-UV-Enhanced Approach for Low-Temperature Solution Processing of IZO Transistors with High-k AlOx/YAlOx Dielectric

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Polarity Control of Top Gated Black Phosphorous FETs by Workfunction Engineering of Pre-Patterned Au and Ag Embedded Electrodes

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

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Characterization and Modeling of Total Ionizing Dose Effects on Nanoscale MOSFETs for Particle Physics Experiments

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Polarity Control of Top Gated Black Phosphorous FETs by Workfunction Engineering of Pre-Patterned Au and Ag Embedded Electrodes

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Deep-UV-Enhanced Approach for Low-Temperature Solution Processing of IZO Transistors with High-k AlOx/YAlOx Dielectric

P-GaN Tri-Gate MOS Structure for Normally-Off GaN Power Transistors

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor