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Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs

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Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs

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A new versatile hybrid MEMS technology for high sensitivity, fluid proof sensing applications.

The Michelangelo step: removing scalloping and tapering effects in high aspect ratio through silicon vias

Integrated multiplexed microwave readout of silicon quantum dots in a cryogenic CMOS chip

Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Memory Systems and Interconnects for Scale-Out Servers

The top-down fabrication of a 3D-integrated, fully CMOS-compatible FET biosensor based on vertically stacked SiNWs and FinFETs

Parallel vs. Serial Inter-plane communication using TSVs