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Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

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Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

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Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks

Parallel vs. Serial Inter-plane communication using TSVs

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

3D-ICE: a Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

3.5-D Integration: A Case Study

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

3D-ICE: a Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Parallel vs. Serial Inter-plane communication using TSVs

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

3.5-D Integration: A Case Study