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A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

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A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

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An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems

High-Speed ADC Design and Optimization for Wireline Links

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

An Event-Based System for Low-Power ECG QRS Complex Detection

Optimized Sampling Rate for Voltammetry-Based Electrochemical Sensing in Wearable and IoT Applications

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

Monolithic technology for silicon nanowires in high-topography architectures

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

Compressed delay-and-sum beamforming for ultrafast ultrasound imaging