Structured analog CMOS design based on the device inversion level

Standard analog design procedure is usually based on a large number of simulations, strongly depends on the type of analog circuit that has to be implemented and requires a lot of manipulation at the transistor level. Simulators offer accurate modeling and precise calculations, but on the other hand ascertaining circuit parameter dependences is difficult and depends on analog designer expertise and knowledge. Moreover, with CMOS technology improvements, the complexity of analog design tasks further increases, since the design specifications become more severe in terms of gain and speed, requiring at the same time minimization of the circuit surface. In this thesis, we propose a structured design approach that allowed us to simplify complex analog design problems and develop a global design strategy that can be used for the design of different analog cells. The basic concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The basic analog structure specifications are derived from circuit-level requirements, and its sizing in the environment imposed by the circuit demands less effort. Furthermore, the procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The transistor-level design procedure is based on the continuous MOS modeling approach and relies on the device inversion level as a fundamental design variable. Since all important design parameters can be expressed as continuous functions of the device inversion level, the design optimum as well as the technology limits can be easily found. Finally, the proposed design procedure is implemented as a CAD tool that guides and assists the user during analog design tasks and provides an interactive interface that allows instantaneous visualization of design trade-offs. At the same time, the user has a great degree of freedom in decision making which enables high human interactivity and design optimization.

Highly sensitive vertical hall sensors in CMOS technology

Enrico Schurig

Vertical Hall sensors are capable of measuring surface-parallel components of the magnetic field. They allow therefore relatively easy conception of single-chip multi-axial magnetic sensors compared to solutions using horizontal Hall plates. The modern trend in the field of Hall sensors is to integrate them into electronic circuitry for signal processing. Before this thesis, highly sensitive vertical Hall sensors completely compatible to a technology adequate for co-integration of electronic circuitry were not available. This is the reason why we present in this thesis the developed knowledge that is necessary for the design and manufacture of highly sensitive vertical Hall sensors in CMOS technology. We first present the principles of the technology choice. A wide selection of CMOS processes is presently available, but in order to obtain optimal sensitivity we have to choose "the right" one. The performances can vary easily by 50% from one technology to another. The best choice are CMOS high-voltage technologies since they deliver n-diffusion layers with relatively low doping level and deep junction depth. We present a novel layout of vertical Hall sensors that has six contacts in the active sensor zone and is a development of the known layout that uses only four contacts. The additional contacts improve the sensitivity and reduce the systematic offset considerably. If we re-use layouts that were optimal for not-CMOS compatible technologies, we will see that the results are not satisfying. We have to develop our specific design parameters that are optimal for the chosen technology. The key for high sensitivities is the strong miniaturization of the devices down to technological limits given by the design rules, but sometimes even beyond that. Some of the design rules can be broken with benefit for the obtained sensor devices. In general, minimum contact sizes and contact distances are preferable as well as a minimum sensor thickness. The difficulty is however to find the absolute minimum before device degradation or even failure will occur. Our optimized sensors achieved voltage related sensitivities of about 0.04 V/(VT) and current related-sensitivities up to 400 V/(AT) that are comparable to existing CMOS compatible horizontal Hall plates. Such sensitivities were never reported for a standard CMOS process, without any additional pre- or post-processing steps. The miniaturization of the Hall devices has however also negative aspects e.g. an increase in sensor offset, noise and output non-linearity. Although Hall sensors have many advantages in comparison to other magnetic sensors (simple structure, low fabrication costs, very good linearity, robustness) they have the drawback of a big Abstract offset voltage that is often too big for many applications. This is why an enormous effort was made by researchers in the past to develop offset reduction methods for horizontal Hall plates. We state in this thesis that, in principle, the same techniques are applicable on vertical Hall sensors but for an optimal efficiency certain principles/parameters have to be respected. We reveal the relations of important parameters as the type of layout (number of sensor contacts), the use of single or coupled sensors, the type of spinning-current, bias level etc. In the optimal case we can obtain residual offset values lower than 200 μT for bias voltages up to 2 V. The spinning current method was originally developed for offset compensation, but it has other beneficial influences on the sensor output signal as well. It is capable to remove a large amount of flicker noise if the spinning is executes at adequately high clock frequencies. We show that the efficiency of flicker noise removal is dependent on the bias current through the sensor. We discovered another positive side effect of the spinning-current method: the elimination of the planar Hall effect. While the planar Hall sensitivity for our sensors is initially about 1% of the normal one at B = 2 T, we obtain with the compensation technique values of only 0.02%. After the presentation of general characteristics of the separate sensors, we present two microsystems based on the developed vertical Hall sensors. At first, we present a 2D magnetic microsystem which is well adapted for the construction of contactless angular encoders with a measurement range of 360°. We profit here especially from the very low offset (< 400 μT) obtained with the spinning current method, since offset is in general the main source of angular errors in such systems. Existing angular measurement systems need in general a special (offset) calibration of the sensor unit in order to achieve an accuracy of 2.5‰ full scale. We obtain such a precision directly with our system for a wide temperature range from -30 to 100 °C. With one specific sensor calibration for the compensation of residual offset, sensitivity mismatch and phase mismatch of the two axes, we attain a precision of about 0.5‰ FS over the same temperature range, a performance never before reported with a magnetic sensor system. The microsystem is therefore an excellent candidate for the majority of low-cost angular measurement applications. As a second example we presented the first fully CMOS integrated three-dimensional Hall probe, consisting of a combination of one Hall plate and four vertical Hall devices. The microsystem allows an application as a universal magnetic field probe in the wide field range from 0.1 mT to 20 T. The probe can be easily used for small volumes because of its small size and the fact that the signal processing circuitry already is directly integrated onto the chip. The precision as a 3D magnetometer is limited by the sensitivity mismatch of about 5% FS. The probe is an ideal candidate for low-cost teslameter applications with limited precision.

EPFL2005

Error handling in multimodal voice-enabled interfaces of tour-guide robots using graphical models

Plamen Prodanov

Mobile service robots are going to play an increasing role in the society of humans. Voice-enabled interaction with service robots becomes very important, if such robots are to be deployed in real-world environments and accepted by the vast majority of potential human users. The research presented in this thesis addresses the problem of speech recognition integration in an interactive voice-enabled interface of a service robot, in particular a tour-guide robot. The task of a tour-guide robot is to engage visitors to mass exhibitions (users) in dialogue providing the services it is designed for (e.g. exhibit presentations) within a limited time. In managing tour-guide dialogues, extracting the user goal (intention) for requesting a particular service at each dialogue state is the key issue. In mass exhibition conditions speech recognition errors are inevitable because of noisy speech and uncooperative users of robots with no prior experience in robotics. They can jeopardize the user goal identification. Wrongly identified user goals can lead to communication failures. Therefore, to reduce the risk of such failures, methods for detecting and compensating for communication failures in human-robot dialogue are needed. During the short-term interaction with visitors, the interpretation of the user goal at each dialogue state can be improved by combining speech recognition in the speech modality with information from other available robot modalities. The methods presented in this thesis exploit probabilistic models for fusing information from speech and auxiliary modalities of the robot for user goal identification and communication failure detection. To compensate for the detected communication failures we investigate multimodal methods for recovery from communication failures. To model the process of modality fusion, taking into account the uncertainties in the information extracted from each input modality during human-robot interaction, we use the probabilistic framework of Bayesian networks. Bayesian networks are graphical models that represent a joint probability function over a set of random variables. They are used to model the dependencies among variables associated with the user goals, modality related events (e.g. the event of user presence that is inferred from the laser scanner modality of the robot), and observed modality features providing evidence in favor of these modality events. Bayesian networks are used to calculate posterior probabilities over the possible user goals at each dialogue state. These probabilities serve as a base in deciding if the user goal is valid, i.e. if it can be mapped into a tour-guide service (e.g. exhibit presentation) or is undefined – signaling a possible communication failure. The Bayesian network can be also used to elicit probabilities over the modality events revealing information about the possible cause for a communication failure. Introducing new user goal aspects (e.g. new modality events and related features) that provide auxiliary information for detecting communication failures makes the design process cumbersome, calling for a systematic approach in the Bayesian network modelling. Generally, introducing new variables for user goal identification in the Bayesian networks can lead to complex and computationally expensive models. In order to make the design process more systematic and modular, we adapt principles from the theory of grounding in human communication. When people communicate, they resolve understanding problems in a collaborative joint effort of providing evidence of common shared knowledge (grounding). We use Bayesian network topologies, tailored to limited computational resources, to model a state-based grounding model fusing information from three different input modalities (laser, video and speech) to infer possible grounding states. These grounding states are associated with modality events showing if the user is present in range for communication, if the user is attending to the interaction, whether the speech modality is reliable, and if the user goal is valid. The state-based grounding model is used to compute probabilities that intermediary grounding states have been reached. This serves as a base for detecting if the the user has reached the final grounding state, or wether a repair dialogue sequence is needed. In the case of a repair dialogue sequence, the tour-guide robot can exploit the multiple available modalities along with speech. For example, if the user has failed to reach the grounding state related to her/his presence in range for communication, the robot can use its move modality to search and attract the attention of the visitors. In the case when speech recognition is detected to be unreliable, the robot can offer the alternative use of the buttons modality in the repair sequence. Given the probability of each grounding state, and the dialogue sequence that can be executed in the next dialogue state, a tour-guide robot has different preferences on the possible dialogue continuation. If the possible dialogue sequences at each dialogue state are defined as actions, the introduced principle of maximum expected utility (MEU) provides an explicit way of action selection, based on the action utility, given the evidence about the user goal at each dialogue state. Decision networks, constructed as graphical models based on Bayesian networks are proposed to perform MEU-based decisions, incorporating the utility of the actions to be chosen at each dialogue state by the tour-guide robot. These action utilities are defined taking into account the tour-guide task requirements. The proposed graphical models for user goal identification and dialogue error handling in human-robot dialogue are evaluated in experiments with multimodal data. These data were collected during the operation of the tour-guide robot RoboX at the Autonomous System Lab of EPFL and at the Swiss National Exhibition in 2002 (Expo.02). The evaluation experiments use component and system level metrics for technical (objective) and user-based (subjective) evaluation. On the component level, the technical evaluation is done by calculating accuracies, as objective measures of the performance of the grounding model, and the resulting performance of the user goal identification in dialogue. The benefit of the proposed error handling framework is demonstrated comparing the accuracy of a baseline interactive system, employing only speech recognition for user goal identification, and a system equipped with multimodal grounding models for error handling.

EPFL2006

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output (I/O) interfaces is subject to much slower growth, due to the limited number of packaging pins and the intrinsic bandwidth constraint of electrical parallel buses. While upcoming serial interfaces provide some relief to this problem in the short term, their data rates remain subject to the inherent bandwidth-distance trade-off in electrical data links. A major move to an optical data link paradigm for very short-distance (board-to-board and chip-to-chip) communications would allow for considerable I/O interface bandwidth enhancement, but this solution currently lacks economic success. Today's optical receivers indeed use compound semiconductor photodetectors in combination with bipolar or BiCMOS amplifiers and CMOS clock and data recovery circuits. The move to fully integrated silicon CMOS receivers would contribute to cost reduction in several ways. Monolithic integration is not only mandatory for optical receivers to become a true I/O interface, it also results in lower volume manufacturing cost, improved yield and reduced assembly and test expenses. The presented work deals with the general problem of monolithic integration and shows the feasibility of fully integrated multi-channel CMOS-compatible fiber-optic receivers for short-distance communications. Multiple challenges, related to the limitations of high-performance analog design in advanced CMOS processes, as well as the combination with a novel silicon photodetector, are addressed. An important realization in this context is that complete integration of the receiver allows for a system-level (global) optimization approach of all components. In this context, we introduce a top-down design methodology propagating the system-level receiver specifications down to the block level, then to the transistor-level. Based on these specifications, transimpedance and limiting amplifier designs are proposed. The limiting amplifier in particular has been designed according to a scaling method for area and power optimization. Magnetic inter-channel coupling effects in multi-channel receivers with inductive peaking have been analyzed, both in theory and by measurement. The clock and data recovery circuit is based on a compact gated oscillator topology and achieves low power and area through partial resource sharing. As this particular topology is not conventionally used for such applications, a novel modeling and verification approach based on statistical and behavioral simulation is proposed. This methodology allows to determine the required power consumption for given jitter specifications and thus results in a power-optimized design. A low-power low-area gated-oscillator clock recovery circuit has been implemented to verify the presented methodology. In summary, a global top-down approach to the design of fiber-optic receivers is presented. Operation of all building blocks at or above the targeted per channel data rate of 2.5Gb/s shows the feasibility of monolithically integrated multi-channel optical receivers in standard CMOS technologies.

EPFL2006

Highly sensitive vertical hall sensors in CMOS technology

Enrico Schurig

EPFL2005

Error handling in multimodal voice-enabled interfaces of tour-guide robots using graphical models

Plamen Prodanov

EPFL2006

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

EPFL2006