A Modular, Direct Time-of-Flight Depth Sensor in 45/65-nm 3-D-Stacked CMOS Technology

This article introduces a modular, direct time-of-flight (TOF) depth sensor. Each module is digitally synthesized and features a 2 $\times$ (8 $\times$ 8) single-photon avalanche diode (SPAD) pixel array, an edge-sensitive decision tree, a shared time-to-digital converter (TDC), 21-bit per-pixel memory, and in-locus data processing. Each module operates autonomously, by internal data acquisition, management, and storage, being periodically read out by an external access. The prototype was fabricated in a TSMC 3-D-stacked 45/65-nm CMOS technology, featuring backside illumination (BSI) SPAD detectors on the top tier, and readout circuit on the bottom tier. The sensor was characterized by single-point measurements, in two different modes of resolution and range. In low-resolution mode, a maximum of 300-m and 80-cm accuracy was recorded; on the other hand, in high-resolution mode, the maximum range and accuracy were 150 m and 7 cm, respectively. The module was also used in a flexible scanning light detection and ranging (LiDAR) system, where a 256 $\times$ 256 depth map, with millimeter precision, was obtained. A laser signature based on pulse-position modulation (PPM) is also proposed, achieving a maximum of 28-dB interference reduction.

SPADnet: a fully digital, scalable and networked photonic component for time-of-flight PET applications

Claudio Bruschini, Edoardo Charbon, Gabor Nemeth, John Richard Walker

The SPADnet FP7 European project is aimed at a new generation of fully digital, scalable and networked photonic components to enable large area image sensors, with primary target gamma-ray and coincidence detection in (Time-of-Flight) Positron Emission Tomography (PET). SPADnet relies on standard CMOS technology, therefore allowing for MRI compatibility. SPADnet innovates in several areas of PET systems, from optical coupling to single-photon sensor architectures, from intelligent ring networks to reconstruction algorithms. It is built around a natively digital, intelligent SPAD (Single-Photon Avalanche Diode)-based sensor device which comprises an array of 8x16 pixels, each composed of 4 mini-SiPMs with in situ time-to-digital conversion, a multi-ring network to filter, carry, and process data produced by the sensors at 2Gbps, and a 130nm CMOS process enabling mass-production of photonic modules that are optically interfaced to scintillator crystals. A few tens of sensor devices are tightly abutted on a single PCB to form a so-called sensor tile, thanks to TSV (Through Silicon Via) connections to their backside (replacing conventional wire bonding). The sensor tile is in turn interfaced to an FPGA-based PCB on its back. The resulting photonic module acts as an autonomous sensing and computing unit, individually detecting gamma photons as well as thermal and Compton events. It determines in real time basic information for each scintillation event, such as exact time of arrival, position and energy, and communicates it to its peers in the field of view. Coincidence detection does therefore occur directly in the ring itself, in a differed and distributed manner to ensure scalability. The selected true coincidence events are then collected by a snooper module, from which they are transferred to an external reconstruction computer using Gigabit Ethernet. We will detail the SPADnet core technologies as well as the latest project achievements in all project areas.

Spie-Int Soc Optical Engineering2014

A CMOS SPAD Imager with Collision Detection and 128 Dynamically Reallocating TDCs for Single-Photon Counting and 3D Time-of-Flight Imaging

Ivan Michel Antolovic, Edoardo Charbon, Scott Anthony Lindner, Martin Wolf, Chunmin Zhang

Per-pixel time-to-digital converter (TDC) architectures have been exploited by single-photon avalanche diode (SPAD) sensors to achieve high photon throughput, but at the expense of fill factor, pixel pitch and readout efficiency. In contrast, TDC sharing architecture usually features high fill factor at small pixel pitch and energy efficient event-driven readout. While the photon throughput is not necessarily lower than that of per-pixel TDC architectures, since the throughput is not only decided by the TDC number but also the readout bandwidth. In this paper, a SPAD sensor with 32 x 32 pixels fabricated with a 180 nm CMOS image sensor technology is presented, where dynamically reallocating TDCs were implemented to achieve the same photon throughput as that of per-pixel TDCs. Each 4 TDCs are shared by 32 pixels via a collision detection bus, which enables a fill factor of 28% with a pixel pitch of 28.5 mu m. The TDCs were characterized, obtaining the peak-to-peak differential and integral non-linearity of -0.07/+0.08 LSB and -0.38/+0.75 LSB, respectively. The sensor was demonstrated in a scanning light-detection-and-ranging (LiDAR) system equipped with an ultra-low power laser, achieving depth imaging up to 10 m at 6 frames/s with a resolution of 64 x 64 with 50 lux background light.

2018

Single-photon image sensors in CMOS

Cristiano Niclass

Among advanced electronic designs, vision systems are perhaps those that have undergone the most dramatic technological revolutions of the last decades. Recently, a new family of vision systems has emerged aimed at three-dimensional (3D) imaging. Many applications exist or will soon come to existence that can use 3D image sensors and the image sensor community is responding with conventional and unconventional solutions. This thesis presents a new concept for imaging and, in particular, for 3D imaging, based on single-photon detection. In our approach, single-photon detection is performed by a device known as single-photon avalanche diode (SPAD). Large arrays of SPADs were demonstrated for the first time in this thesis and time resolutions consistently in the picosecond range were achieved. It has thus become feasible to design solid-state 3D imagers with millimeter depth perception based on the time-of-flight principle. Initially, large arrays of SPAD devices and associated circuitry have been investigated in a 0.8µm CMOS technology. Extremely low-noise detectors were implemented in this technology. In arrays of 64x48 pixels, the median dark count rate was 0.5Hz per square micrometer of active area. For these devices, the maximum photon detection probability was 26% at 550nm optical wavelength. Subsequently, a technology migration of SPADs towards deep-submicron CMOS has been successfully achieved. For the first time, SPADs in 0.35µm and 0.13µm CMOS technologies were designed and characterized. Outstanding photon detection probabilities up to 35.4% and 34.5% have been measured in devices manufactured in 0.35µm and 0.13µm CMOS, respectively. Median dark count rate has increased with technology scaling. The median dark count rate over an array of 128x128 pixels was 18 Hz/µm2 in 0.35µm CMOS, whereas it was 385Hz/µm2 in 0.13µm CMOS for a single device. With the aim of enabling high-performance system-on-a-chip implementations using single-photon detectors, appropriate front-end and ancillary circuits utilized in the detection, measurement, and storage of time-of-flight evaluations have been introduced. For the first time, passive quenching circuits using a single MOS transistor were investigated. Based on the proposed biasing regime, the single MOS quenching circuit provides well defined dead time and leads to high pixel fill factor. Active recharge is achieved in this thesis by means of a new dual-threshold quenching and recharge circuit. This circuit allows the implementation of a hold-off time using low in-pixel transistor count, thus improving afterpulsing probability with little or no penalty in fill factor. 3D image sensors based on a pulsed detection technique known as time-correlated single-photon counting (TCSPC) have been investigated. Moreover, a technique has also been investigated for range imaging using SPADs that operate with continuously modulated optical signals. This technique, known as single-photon synchronous detection (SPSD), was invented in the course of this thesis and it is introduced here for the first time. In order to demonstrate the potential of TCSPC in solid-state 3D imaging, a complete theoretical and experimental investigation was conducted. An analytical model for the evaluation of ranging performance based on TCSPC was introduced. A fully-integrated TCSPC system for single-photon time-of-flight evaluation was implemented in CMOS, for the first time. Depth maps of 3D scenes were achieved at millimeter precisions using only 1mW of laser power and an integration time of 50ms. Thanks to SPAD technology, accurate distance measurements are now possible even with extremely low photon count rates of a few thousand per second. The maximum non-linearity in distance measurement was 9 millimeters over the full measurement range. Time-varying uncertainty (1σ) at the farthest distance was 5.2 millimeters. The SPSD approach has been theoretically and experimentally investigated. The design of the first fully-parallel implementation of a single-photon image sensor in CMOS has been introduced. The sensor has enabled the acquisition of real-time 3D images, based on CMOS SPADs, for the first time. A 3D camera prototype was designed and built based on the SPSD image sensor with a field-of-view of 50°. Experimental results showed that the SPSD rangefinder is effective. Distance measurement performance was characterized with a maximum non-linearity error of 11cm within a range of a few meters. In the same range, the maximum repeatability error was 3.8cm.