Simulation of Instability in Time-Sensitive Networks with Regulators and Imperfect Clocks

Regulators are used in time-sensitive networks in order to reshape traffic reducing the burstiness generated by the aggregation systems within the network. Regulators, in terms of the IEEE TSN group are defined as Asynchronous Traffic Shaping or what in the literature is known as interleaved regulators. These regulators are placed before a multiplexing stage, shaping the outgoing traffic and cancelling the increased burstiness, allowing calculations of the worst-case delay to be performed. One of the main properties studied for regulators implies that they do not increase the worst-case delay in the network. So far, all the studies were performed assuming ideal clocks within the network. However, a recently published paper underlines the importance of taking into account non-ideal clocks while studying interleaved regulators properties, providing a theoretical proof that under certain circumstances, interleaved regulators can lead to system instability due to the unbounded delay through them. This thesis intends to continue with this study, providing a simulation proof that shows instability when interleaved regulators are simulated assuming non-ideal clocks. This is carried out in the network simulator ns-3. Along with the different developed modules, two are highlighted: local time and ATS modules. The former introduces the notion of local times in ns-3, whereas the latter implements regulators functionality in ns-3, following the implementation proposed by the IEEE TSN.