Fault Collapsing in VLSI Systems

Related lectures (19)

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Covers the Logical Effort method for optimizing logic delay and gate sizing impact.

Explores defects, errors, and fault models in VLSI systems, emphasizing fault collapsing and dominance.

Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.

Introduces SCOAP measures for testability analysis in VLSI systems, covering controllability, observability, and test vector length prediction.

Explores logical effort, optimum sizing, and branch efforts in VLSI design.

Explores test vector generation, ATPG algorithms, fault coverage, and path sensitization in VLSI systems.

Covers Advanced VLSI Design concepts, including Full Custom Design and Parallel Prefix Adder.

Explores the significance of power and energy in VLSI design, covering topics like power reduction, energy efficiency, and voltage scaling.

Covers the generation of test vector patterns, fault modeling, structural vs. functional tests, and the implementation of time-frame expansion.

Covers the fundamentals of VLSI design, focusing on the semi-custom design flow.