MEMS Packaging: 3D Integration & Advanced Technologies

This lecture covers advanced MEMS packaging technologies, including 3D integration, wafer-level packaging, through silicon vias, and hermetic packaging. It discusses the benefits of 3D integration, the differences between 2.5D and 3D integration, and the fabrication processes of TSVs. The instructor explains the importance of hermetic packaging, materials used, bonding techniques, and the role of getters. Various packaging techniques such as surface bonding, anodic bonding, and eutectic bonding are explored, highlighting their advantages and drawbacks. The lecture also delves into the challenges of gas leakage characterization in hermetic packaging and the need for compact systems through chip-level 3D solutions.

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In depth analysis of the operation principles and technology of advanced micro- and nanosystems. Familiarisation to their implementation into products and their applications.

Three-dimensional integrated circuit

A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

System in a package

A system in a package (SiP) or system-in-package is a number of integrated circuits (ICs) enclosed in one chip carrier package or encompassing an IC package substrate that may include passive components and perform the functions of an entire system. The ICs may be stacked using package on package, placed side by side, and/or embedded in the substrate. The SiP performs all or most of the functions of an electronic system, and is typically used when designing components for mobile phones, digital music players, etc.

Quad flat package

A quad flat package (QFP) is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common. Other special variants include low-profile QFP (LQFP) and thin QFP (TQFP). The QFP component package type became common in Europe and United States during the early nineties, even though it has been used in Japanese consumer electronics since the seventies.

Integrated circuit packaging

In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board. In the integrated circuit industry, the process is often referred to as packaging. Other names include semiconductor device assembly, assembly, encapsulation or sealing.

Through-silicon via

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

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